Re: Testbench Automation
s_vlsi said:
No I am not looking for regression.
ok i will clarify myself.
when we are checking for data integrity and packet is small in size then
by looking on the waveform we get to know,but if packet size is big say 3000-
4000 bytes of data is there then checking on waveform is prone to errors.
That is why i wanted to ask if instead looking on the waveform is there any other
way is there or not.
Regards
What you need to develop is called a "scoreboard" in Verification. It essentially does the following: (Here SV refers to SystemVerilog)
1. Keeps track of incoming packets (Use SV Queue to store it)
2. Whenever an output packet appears, it pops an elemtn from the packet queue
3. Passes it through a reference algorithm (that you should have modeled using higher level constructs such as in SystemVerilog) and makes an "expected packet"
4. Compares the expected and the actual and declares pass/fail
This is an involved job and requires a while to get it right, but the benefits are far encouraging than the time spent.
ALso as some one else mentioned, assertions are a good choice too. If it is a simple, not deeply pipelined design, then a simple assertion such as:
Code:
property p_data_intg;
int my_local_pkt; // assume pkt is of 32 bits, if not change this
@(posedge clk) $rose(start_of_pkt), my_local_pkt = in_pkt |=>
[1:100] $rose(out_pkt_start) && my_local_pkt == out_pkt);
Will do the job for you. Above code is using SystemVerilog Assertion, not compiled for correctness - just to give you an idea.
BTW, there is more automation that you can do in generator side, you may want to look at VMM kind of methodology. We just finished writing a book on adopting VMM in real life designs. See details in signature below.
Good Luck
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/[/list]