How to assign vectors to array in VHDL

[xilinx1001]

Hi,

I need to give two 9 bit values(cm, cm2) to an array

cm and cm2 contains the two 9 bit values

I am doing something like this which is not working

TYPE matrix IS ARRAY (0 TO 2) OF STD_LOGIC_VECTOR(8 DOWNTO 0); --type definitions
SIGNAL x: matrix; --signal declarations

matrix(0)<= cm,
matrix(1)<=cm2

Can you suggest anything about this?


Regards
xilinx1001

 

[barry]

That looks almost right, assuming cm and cm2 have been declared as std_logic_vector(8 downto 0). You need to terminate your assignment statements with ";", not ",".

What errors are you getting?

 

[xilinx1001]

Hi,

I am getting the errors like this

Line 246. The expression can not be converted to type matrix.
Line 247. The expression can not be converted to type matrix.

Actually I need to display the two 9 bit values continuously in a circular sequence

For thatI am actually thinking of some thing like this:

code:

begincountClock: process(CLK, count)
begin
if rising_edge(segclk) then
if count < "10000000" then--creating a delay of 0.02 seconds and 50 hertzs
a<=cm;
else
if count < "20000000" then
a<=cm2;

count<=(others=>'0');
end if;
end if;
end if;
end process;

 

[aria62]

1. The code you wrote dosen't create a delay at all. before you use the expression "count<10000000" you should make the count signal to increase with every clock edge.in other words you should make a clock counter.

2.it seems that the error is because of a type mismatch. please send line 246 and 247 of your code. by the way which libraries did you evoke at the beginning of the code?