How to assign output signal in an array in VHDL?

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Ngised

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I have a matrix with rows and columns of XOR, n x m. In the first output I want to assign the output with a signal to the first row.
How I am going to do that?

Code: 
type matrix is array(0 to n-1) of std_logic_vector(m - 1 downto 0);
    signal out_vec : matrix;
 
begin

for i  in 0 to n-1 generate
XI:xor_gate
port map ( x => op_x(i),
           y => op_y(i),
        output => out_vec(0)  -- it doesn't work
);
end generate;
 
end architecture ;
 
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What do you mean. “it doesn’t work”? Does it fail synthesis? Does it generate an error message? Does it make strange noises?

Also, you don’t give a clue as to what xor_gate is. What is the dimension of output?
 

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The dimension of the output is a range 3 to 8, the max size of the array is 8 x 8. A xor_gate is a xor gate. It doesn't work means it's not recognized and it is red underlined an error will be occurred if I synthesize it.
 

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If the output of xor_gate is one-bit, and then you are trying to assign it to a vector of (m-1 downto 0), that's a problem.

output=>out_vec(0) is assigning 1 bit to a (m-1 downto 0) slv.

Further, you are assigning values to out_vec(0) over and over again in your generate statement. I think you need an index into out_vec, not a 0.
 

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Ngised said:
The dimension of the output is a range 3 to 8, the max size of the array is 8 x 8. A xor_gate is a xor gate. It doesn't work means it's not recognized and it is red underlined an error will be occurred if I synthesize it.
Click to expand...
Let's see your declaration for output. Like barry has suggested, also look at the indexing of out_vec.
 
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