How to Apply AREA_GROUP constraint for a component in a hierarchical design

Hello,

I am using ISE 14.7 to implement my design. My design includes some modules that are inside another modules and created a hierarchical design. For example, my main design has a DUT1 and a DUT2 connected together.
DUT1 includes module_1, module_2 and modulle_3 and also DUT_2 includes module_4, module_5 inside itself.
Now, I want to specify an area to put each module in a specific place in floorplan. I wrote the following command in UCF but it returns the following error !! I am confused whether we can use the AREA_GROUP command for such a hierarchical design and if yes, how?
Kind helps are cordially appreciated.


INST "module_1" AREA_GROUP = CIRCUIT1;
AREA_GROUP "CIRCUIT1" RANGE = SLICE_X0Y50:SLICE_X3Y56;


------
ERROR:ConstraintSystem:59 - Constraint <module_1" AREA_GROUP =CIRCUIT1;>
[sources/top.ucf(31)]: INST "module_1" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.


I also did the following trials, but I got the same error:

INST "DUT1/module_1" AREA_GROUP = CIRCUIT1;
AREA_GROUP "CIRCUIT1" RANGE = SLICE_X0Y50:SLICE_X3Y56;


INST "DUT1/Inst_module_1" AREA_GROUP = CIRCUIT1;
AREA_GROUP "CIRCUIT1" RANGE = SLICE_X0Y50:SLICE_X3Y56;





Thanks and Regards,