How to analyze power consumption in this low power design?

[arunragavan]

Low power Design

ello guys..

Well the concept of low power can be explained by factors such as

Switching, shortcircuit, leakage and static --

Keeping these factors in mind, i propose to design a VLIW processor which wud be under the Globally Asynchronous and Locally Synchronous technology(GALS) ,

First i have to design an ALU which can perform basic operations such as multiplication( shift and add (or) booth multiplier) divison - sub - exponential etc.

and at first build a set of 4-5 ALUs and there by make it work to achieve paralellism..my basic design shud involve complexity in complier and simple hardware design.

my entire point is -- how do i analyze the power consumed by ALU - (one ALU under GALS) and a set of 4 ALUs pipelined which again are under GALS.

How do i go about it?

1: ) Should i design the ALU get the synthesis.. the schematic with leonado spectrum -- find the area, delay optimization results.. and then go in for optimization manually.

2: ) should i let the software optimize for me

3: ) OR GUYS just help me out.. am jes confused.. wot shud i be doing..

am confused..

 

[funzero]

Re: Low power Design

gating clock is good for rtl design. if you still want to lower your power consuption, find a special designed library

 

[yeewang]

Low power Design

manual work always does more than tool.
architectural optimization works better than low-level.

 

[arunragavan]

Re: Low power Design

umm thats alrite... i also think its always better to have a manual optimization.. our lab aint equipped with good optimization tools.. all that we have is modelsim. thats ok for very simple level of abstration.. i need to do power analysis.. like design a FU - with simple ALU units.. measure the power consumed by each of the FU when clocked seperatly -- asynchronous..

wot do u ppl think i shud start off with...

please be free to share ur thoughts..

 

[masai_mara]

Re: Low power Design

I think based on the hardware each of the ALU's is going to consume so much power so its better to optimize each of them individually rather than combined optimization. So primarily you have to start with architecture favouring low power which also means having low gate count, then you could achieve further optimizations with a library designed for low power and do some more manual tweaking during synthesis to constrain power. It would certainly help you if you had specific vendor tools like prime power etc.

 

[arunragavan]

Re: Low power Design

thats wonderful.. so i think i shud start of with a baic ALU design.. synthesis it.. and go in for optimization manually so that i can easily reduce the gate count to attain minimum powerfor each instance...

Prime power, i heard of it.. lemme try to get my hands on it..

thanks..

help me further on..

 

[flypig]

Low power Design

I think that if the architecture is more important for the ALU design. If u can not focus on the speed, that wud have some pretty architecture. and The Full-custom design flow is better for u! Such as Prime time , powermill and pathmill can be used.
good luck !

 

[arunragavan]

Re: Low power Design

yeah my design wud be fully customed.. thats alrite when it comes to low power application the tradeoff wud be obvious reduced speed and efficiency of operations.. wot do u think might be an alternative...

i dunt have access to these tools.. power mill etc etc.. am jes helpless...

keep me still pondering..

 

[haoboy]

Low power Design

can anyone say something more about gating clock?

 

[arunragavan]

Re: Low power Design

Clock gating is a method to reduce power.

Improving clock-gating for saving power

The gate count of ASICs is increasing drastically while factors such as area, cost & power are decreasing. Nowadays RTL coding is not restricted to front-end design as it used to be and designers are equally concerned with issues such as layout & power consumption.

Though Clock Gating is a well-known concept for power saving, for technologies below .18 µm mere switching OFF of the clock is not good enough. For maximum power saving the data toggle also needs to be switched OFF with the clock. While tools such as Power Compiler are smart enough to know which signal is to be used for Clock Gating, they are still not intelligent enough to change the architecture of the RTL code.

If a gating element is added in the flop then the implementation will save more power then the implementation without the gating element since the data input to the flop will only be toggled when required.


This is the main advantage of using clock gating.

 

[zhangpengyu]

Low power Design

I heard that synthesis tool could support gating
clock now,so more designer use gating clock to do low power design.

 

[tukken]

Re: Low power Design

prime power is good choice

 

[arunragavan]

Re: Low power Design

could anyone enlighten me about prime power.. and clock now tools.. details..

with regards,

 

[Arik]

Re: Low power Design

Hi All,

in fact Synopsys has 2 major products intended for front-end power analysis/optimisation:

1. Power Compiler - which is integrated in DC environment and also could be used as a separate tool for RTL power estimation only calling pe_shell from shell. Power Compiler allows to do power analysis and optimisation both on RTL and gate levels. Power Compiler supports several techniques for power reduction such as clock gating, operand isolation, multi Vth libraries.

2. PrimePower - is a fully separate product. It allows to do more detailed power analysis, but it doesn't support power optimisation.

You can find more info on both products in the Solvnet !!!

 

[shelkerahul]

Re: Low power Design

Hi all,


Clock gating is very good point in low-power design. I want to add a last but not least point is REDUCE the frequency if possible OR be sure that all the flop should not toggle at a time ( I mean reduce the no. of F/F switching at a time as much as possible) these things u need to consider at a time of architecture.

RAHUL