How to add unisim and unimacro library in vcs simulation ?

[dharag]

Hello,

I am new to VCS, I am using VHDL DUT and system verilog environment for verification. my vhdl code uses unisim and unimacro libraries so how to include those libraries in vcs and simulate ?

Also what are the steps or commands to use this VHDL libraries in VCS ?

 

[sharath666]

Just compile the verilog files under unisim and unimacro libraries into the sim environment. That should do I suppose..

 

[dharag]

Hello Sharath,

Thanks for your reply. I have mapped the libraries but error coming is of missing library components. So i think i have to recompile these libraries in xilinx and choose VCS as simulator. my query is does linux version of XILINX support VCS simulator and can compile libraries for VCS ??

Thanks in advance

 

[sharath666]

Although I have personally not worked on VCS with xilinx,I don't see why it shouldn't...

 

[ads-ee]

dharag, If the xilinx compxlib tool doesn't compile for VCS then you'll have to manually compile the libraries. Manual compilation is not necessarily simple. I've had to do this on more than one occasion when the compxlib didn't work (crashed) on my windows machine. If you compile some of the files in the incorrect order you can see issues with reported missing components. Also make sure you don't forget to compile the glbl.v file if you are using the verilogg libraries.

regards

 

[dharag]

hello ads-ee,

I am working on linux machine and dnt know how to compile vhdl libraries for VCS, as my DUT is in VHDL and verification language I am using is system verilog. Can you tell me how to compile vhdl libraries of xilinx for vcs simulator on linux redhat machine ?

 

[ads-ee]

have never used vcs can't tell you what commands to use to compile the libraries. The simplest method may be to compile all the vhdl files in unisim and unimacro directories from a command line script and reorder any files that have dependencies on other files, when if fails to compile. It will probably take a few iterations to successfully compile everything, just make sure you don't have any compilation errors when you run the script for the last time.

 

[dharag]

Thanks ads-ee

I have installed trial version of xilinx on linux machine, I wanted to know the compxlib command for library compilation for VCS simulator.
Also does xilinx support library compilation for trial 30 day version ??

 

[ads-ee]

If they have a command for VCS then you'll have to look it up in the documentation. I've always used modelsim on either windows (primarily) and linux (occasionally). If you have a true trial version of the tools (not web pack) then it should have everything that the full purchased tool suite has. In the past I've had to use the trial versions while waiting to have softwre keys purchased.

Regards

 

[dharag]

Anyways I would check for the same, Thanks ads-ee for your support

Regards,
Dhara

 

[dpaul]

DIGGING UP THE OLD THREAD....

Hi dharag,
were you able to find a solution to the problem?

Actually I am facing a similar problem now, while integrating a VHDL Xilinx IP in a Verilog top-level design and compiling with VCS.

I have created a separate filelist and compiling whatever us under unisims ans unimacro.
# VHDL unisim and unimacro
vhdlan -full64 -f $HW_TOP/sim/scripts/filelist_vhdl_lib.txt
(I am compiling everything under /primitive)

dpaul@crest:/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims$ ls
primitive secureip unisim_VCOMP.vhd unisim_VPKG.vhd
dpaul@crest:/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unimacro$ ls
ADDMACC_MACRO.vhd COUNTER_LOAD_MACRO.vhd MACC_MACRO.vhd
ADDSUB_MACRO.vhd COUNTER_TC_MACRO.vhd MULT_MACRO.vhd
BRAM_SDP_MACRO.vhd EQ_COMPARE_MACRO.vhd unimacro_VCOMP.vhd
BRAM_SINGLE_MACRO.vhd FIFO_DUALCLOCK_MACRO.vhd
BRAM_TDP_MACRO.vhd FIFO_SYNC_MACRO.vhd

But still I have the following errors (AFIFO36_INTERNAL.vhd is the first file under /unisims/primitive):

Parsing design file '/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd'

Error-[XSYMTABNOLIBMAP] Missing library map
  Library logical name 'UNISIM' is not mapped to a host directory.
  The show_setup command shows all of the mappings for the libraries.  Please 
  use this command to validate that the named library above is mapped to a 
  physical directory in your synopsys_sim.setup file.


Error-[OVNOSELECT1_LIB] Undefined identifier
/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd, 46
AFIFO36_INTERNAL
  
  use unisim.vpkg.all;
             ^
  The symbol named 'VPKG' cannot be found in library 'UNISIM'.


Error-[OVNOSELECT1_LIB] Undefined identifier
/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd, 47
AFIFO36_INTERNAL
  
  use unisim.vcomponents.all;
             ^
  The symbol named 'VCOMPONENTS' cannot be found in library 'UNISIM'.


Error-[IEEEVHDLNOENT] Missing compiled design unit
/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd, 94
analysis-Parsing, "AFIFO36_INTERNAL"
  
  architecture AFIFO36_INTERNAL_V of AFIFO36_INTERNAL is
                                     ^
  The compiled design unit for entity 'AFIFO36_INTERNAL' is not found in WORK 
  library.
  Please verify that the entity was analyzed successfully.

"/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd": errors: 4; warnings: 0.
.
.
.
MORE UNISIM based errors!

Can anyone please tell me what VHDL libraries should I be compiling in order to use the Xilinx VHDL IP (AXI_IIC_v1.02a)?

Right now I am trying to compile VHDL libs under WORK. Is this the correct approach (I doubt it)? In that case, should the Xilinx VHDL libs be compiled in a separate dir and then it needs to be mapped somehow?

 

[dpaul]

ok, I have found out how to compile the Xilinx VHDL libs prior to parsing the VHDL design files using the VCS vhdlan command.

compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir /home/dpaul/rtl_work/xilinx_vhdl_libs -l vhdl -lib all -log /home/dpaul/rtl_work/xilinx_vhdl_libs_compile.log

Note that I am using a new logical library named 'XILINX_VHDL_LIBS'

Now while compiling with VCS I get the 1st error as...
vhdlan -full64 -work xilinx_vhdl_libs -f filelist_te0630_vhdl.txt

Error-[VHDLNOWORK] Missing library mapping
  Logical library name 'XILINX_VHDL_LIBS' is not mapped to a physical 
  directory.
  The show_setup command shows all of the mappings for the libraries.  Please 
  use this command to validate that the named library above is mapped to a 
  physical directory in your synopsys_sim.setup file.

Can anybody tell me how to map this newly created logical library to the physical library?

 

[hepipatel]

Dear dharang,
To simulate vhdl libraries you have to make some changes in synopsys_sim.setup file.You have to map logical library with physical library in synopsys_sim.setup file.The syntax is like.Logical library : Physical Library.After than with the help of show_setup command you can see your library mapping.After do this you can use vhdlan command,vcs command and simv command.

 

[hepipatel]

In synopsys_sim.setup file you have to make changes in which you have to add logical library and physical library in this format:
Logical Library : Physical Library

- - - Updated - - -

ok, I have found out how to compile the Xilinx VHDL libs prior to parsing the VHDL design files using the VCS vhdlan command.

compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir /home/dpaul/rtl_work/xilinx_vhdl_libs -l vhdl -lib all -log /home/dpaul/rtl_work/xilinx_vhdl_libs_compile.log

Note that I am using a new logical library named 'XILINX_VHDL_LIBS'

Now while compiling with VCS I get the 1st error as...
vhdlan -full64 -work xilinx_vhdl_libs -f filelist_te0630_vhdl.txt

Error-[VHDLNOWORK] Missing library mapping
  Logical library name 'XILINX_VHDL_LIBS' is not mapped to a physical 
  directory.
  The show_setup command shows all of the mappings for the libraries.  Please 
  use this command to validate that the named library above is mapped to a 
  physical directory in your synopsys_sim.setup file.

Can anybody tell me how to map this newly created logical library to the physical library?

Reply:-
You have to do the following:
XILINX_VHDL_LIBS : Physical Library(Here you have to provide path where this library is located)