[SOLVED] How to add decoupling cap for a 0.6V-VDD, leakage sensitive IC?

[czq1419]

Hi,
My analog VDD is 0.6V(core circuit in subthreshold) and I'm using 0.18um process, and my AVDD current is on the order of 10uA, so I do care about any leakage. How to properly add some decoupling caps between AVDD and AGND?

For NMOS core device (tox is 4nm), I worry that the gate leakage current would be too large(although it is 0 by simulation but I'm not sure what is the real value); for NMOS IO device(tox is 6nm), the leakage is smaller but it's Vth is ~800mV and my AVDD is not enough to turn it on. How to deal with this?

 

[crutschow]

Polypropylene film capacitors have low leakage.

 

[mtwieg]

Are you talking about decoupling capacitors on the die (MIM, MIP, etc), or external capacitors? Your typical ceramic capacitors will typically have insulation resistances on the order of 10Mohm or more, so leakage should be insignificant.

As for your second question, if your threshold voltage is less than Vdd then you are sort of screwed, especially for io driver stages. Maybe your process can include an implanted threshold adjustment step?

 

[czq1419]

Hi mtwieg,
I'm talking about on-die decoupling caps using MOSFET caps, not ceramic ones, and I'm worrying about the the tunneling current through the gate oxide, so I wonder what's the order of magnitude.
As for IO driving, I have a 3.3V on IO ring and all digital IO cells have built-in voltage level shifters.(either 3.3V to DVDD or DVDD to 3.3V)

 

[mtwieg]

MOS cap leakage is quite hard to predict without intimate knowledge of the process... you'd be best off getting that information from the fab house. From what I recall, at tox=4nm you're starting to get into the regime where tunneling starts to become significant, but it's only at tox<3nm that it really starts to become dominant. How much capacitance do you actually want?

 

[czq1419]

I just added caps where there is free space. The total area is about 40000 um square. Generally, will the leakage of this one reach 1uA? My gate voltage is quite low, so I guess the gate tunneling leakage won't be that serious.

 

[erikl]

I just added caps where there is free space. The total area is about 40000 um square. Generally, will the leakage of this one reach 1uA? My gate voltage is quite low, so I guess the gate tunneling leakage won't be that serious.

Right. Here's a figure on Tunnel Current Density vs. Oxide Voltage from this paper.



Up to these results, your 40k(µm)² cap will add a tunnel current in the order of a pA only.

 

[czq1419]

OK, very kind of you