I'm guessing you are talking about a wire data type in verilog.
if it is so, my suggestion would be to constrain it as a combinational logic. i've heard that virtual clocks can be used to constrain combinational logic.
YEah virtual clocks can be used to constrain combo logic ......
how shud I constrain it as COMBINATIONAL logic???
U mean placing all combo in one module???
i'm not sure i follow. my understanding is, we use a virtual clock and use that to specify the delay values. i think we specify set_max_delay and set_min_delay.