Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ex00 is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; lval : out STD_LOGIC; dval : out STD_LOGIC); end ex00; architecture Behavioral of ex00 is signal count_div_16 : std_logic_vector(3 downto 0); signal count_1000 : integer range 0 to 999; begin clk_div_16 : process(clk, reset) begin if reset = '0' then count_div_16 <= (others => '0'); elsif (clk='1' and clk'event) then count_div_16 <= count_div_16 + "1"; end if; end process; cntr_1000 : process(count_div_16(3), reset) begin if reset = '0' then count_1000 <= 0; elsif falling_edge(count_div_16(3)) then --rising_edge??? if count_1000 = 999 then count_1000 <= 0; else count_1000 <= count_1000 + 1; end if; end if; end process; dval <= count_div_16(3); lval <= '1' when (0 <= count_1000 and count_1000 < 256) else '0'; end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY ex00_tb IS END ex00_tb; ARCHITECTURE behavior OF ex00_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ex00 PORT( clk : IN std_logic; reset : IN std_logic; lval : OUT std_logic; dval : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; --Outputs signal lval : std_logic; signal dval : std_logic; -- Clock period definitions constant clk_period : time := 62.5 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ex00 PORT MAP ( clk => clk, reset => reset, lval => lval, dval => dval ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; reset <= '1'; wait for clk_period*10; -- insert stimulus here wait; end process; END;
yes.......Line valid(LVAL) ---> On time= 256 usec and OFF time = 744 usec continuously ?
yes.......Data Valid(Dval) ---> --- falling edge of dval going with lval raising (On time = 0.5 usec and Off time = 0.5 usec) continuously?
how you had created???? which tool you made it from??? and i do not understand this RTL because LOW resolution image........I had created the rtl schematic for the vhdl code which you had sent.
is yuor rtl refer to my vhdl????????????I had created the rtl schematic using Xilinx ISE 10.1.3. Please check this one which i attached.
signals in the Schematic which you posted doesnt match your vhdl code. Refere that, which you attached schematic is matching with the vhdl code which you posted,? Please let me know.
i know.... you are working with version 10.1, but i am working with 13.2........I dont know why your rtl schematic doesnt match my rtl schematic
xilinx ISE made these signals itself like madd_count........there are many signals like madd_count is not used in the vhdl code you posted.
i do not know how it is working in version 10.1...... but i think you are in right way......check this for how i created that rtl:
In xilinx ISE 10.1.3 project nagivator --> in process window --> synthesize- XST option --> under view rtl schematic to obtain rtl schematic
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