Hi
I've written a testbench for my design in vhdl but I don't know how to access the internal signals of my DUT. Is it possible or we can only have access to the ports? If yes, please help me with the syntax.
You can use
'init_signal_spy' if you are using modelsim.
this will allow you to access internal signals from your testbench, and then you may write them into a file.
for full syntax see modelsim guide or search in goolge for 'init_signal_spy'
Kr,
Avi http://www.vlsiip.com