How the design a frequency doubler

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bigpop

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Hi anybody

I want double my input clock frequency. Except use PLL, is there any other circuit can realize this function?
My input clock frequency is 250Mhz, output clock duty cycle shold be 40%~60%, propagation delay should be <2ns.

thanks very much
 

there is a simple solution.... give the clock to a buffer and then AND the original clock signal and the buffered signal... due to the delay the AND gates output is a signal with double the frequency and the duty cycle can be adjusted based on the propogation delay of the buffer....
 

use an xor and us it in feedback in a delay locked loop to maintain duty cycle of 50%
 

thanks amarnath and Srinivasan. I will try to use this way
 

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