How should I connect substrate of 1.2V and 3.3V?

[brakchus]

Hi, I'm working on layout of IO buffer and wondering how is connection of 1.2V and 3.3V nmos transistors to substrate realized? If 1.2V and 3.3V nmos transistors are connected to the same substrate, how does it has to esd reliability? Pmos are connected to separated nwells. I'm using UMC 130nm. Should I connect nmos to sub using twell?

 

[erikl]

... Should I connect nmos to sub using twell?

Why not use nmos directly on substrate? I guess you need nmos in twell only for stacked nfets, or for special RF or HV applications. For I/O's I think the nmos should be on substrate.

 

[brakchus]

1.2V nmos is core transistor for core and i/o circuits (1.2V connection to Vdd core and Gnd core). 3.3V transistors are only for i/o's (connected to Vdd i/o and Gnd i/o). Connecting both kind of nmos will short circuit both grounds and I wondering is it appropriate method? For esd reliability in in i/o ring separated power/ground lines are provided and short circuiting them seems to be not the best solution.

 

[erikl]

... For esd reliability in in i/o ring separated power/ground lines are provided and short circuiting them seems to be not the best solution.

Ok. Each foundry uses its own ESD rules and methods. Best solution is to follow the suggestions of your PDK re. IO power connections.

 

[dipak.rf]

For NMOS dont see any problem if you connect both the ground to common substrate of 1.2V and 3.3V devices. For PMOS anyway you are connecting both the NWELLs at different potential

For ESD you should go by recommanded structure by foundry itself

 

[deepak242003]

Hi, I'm working on layout of IO buffer and wondering how is connection of 1.2V and 3.3V nmos transistors to substrate realized? If 1.2V and 3.3V nmos transistors are connected to the same substrate, how does it has to esd reliability? Pmos are connected to separated nwells. I'm using UMC 130nm. Should I connect nmos to sub using twell?

I believe you will be having seperate ground buses in your ring for ESD and core circuits.. your can connect respective grounds.

As Eric1 point, twell not required for this case..

 

[brakchus]

I believe you will be having seperate ground buses in your ring for ESD and core circuits.. your can connect respective grounds.

Yes, seperate buses are available in io ring. The question that I've got is about substrate of nmos transistors. I prepared some picture to illustrate my doubt better:

**broken link removed**

So the question is: if I connect nmos transistors grounds to seperated ground buses (i.e. nmos1 to gnd_io bus and nmos2 to gnd_core) and bulk pins of transistors to respective substrates (nmos1 to gnd_io and nmos2 to gnd_core) would I have both grounds shorted as a result (both substrates are as a matter of fact the same substrate)?

 

[laststep]

I believe every foundry have its own spacing that you need to follow when using diff voltage for the substrate. Also if you notice each thick oxide device (3.3V) have a guarding surround it to pick up the substrate noise so that it wouldn't affect others device.

So the ground eventually is not short together, they are separate by resistor (p-sub resistance), passive diode (guard ring).

Just my 2 cent, correct me if i'm wrong

 

[alvays]

Brakchus:

In chip core, different powersupply blocks can be enclosed with p diffusion of their own power