How PT calculates setup and hold time between 2 FF clocked by two different clocks?

[lokesh_boddu]

Hi friends

i have the following questions. Thanks in advance for answering.

1. How PT calculates setup and hold time between 2 FF clocked by two different clocks?
2. When we use set_max_delay and set_min_delay , the delay calculated by the PT is over ridden, so what will happen to the data path( like will PT add “buf” to it)? How PT ensures the time will not exceeds the limit set using the above commands?
3. Calculate Min clock frequency at which the circuit can function?


Regards
Bdu

 

[flexible100]

Re: doubt related to STA

If the two clocks are not multiples of each other, there is no fixed phase relationship with each other.
Therefore, a signal clocked by the first may appear at any time within the clock period of the second.

This is a standard clock domain crossing. You need to exclude these from your STA analysis.

There are other methodology and design tools that are used to ensure that the CDC is done properly.

 

[huckle]

Re: doubt related to STA

If the two clocks are not multiples of each other, there is no fixed phase relationship with each other.
Therefore, a signal clocked by the first may appear at any time within the clock period of the second.

This is a standard clock domain crossing. You need to exclude these from your STA analysis.

There are other methodology and design tools that are used to ensure that the CDC is done properly.

@flexible100: If the two clocks are not multiples, still there IS a worst case for the CYCLE ADJUST.

 

[flexible100]

Re: doubt related to STA

Sorry, I dont know what you mean by cycle adjust.

When 2 clocks have a constant phase, (same clock or multiple of each other), then STA makes sense. It checks that the
cone of logic between the 2 flops has low enough delay that the signals arrive at the second flop with enough setup
time.

When the phases are continuously changing, STA does not make sense anymore. At least in the sense of setup/hold
analysis. So I would be interested in hearing more details about cycle adjust that you mention.

 

[jeevan.life]

Re: doubt related to STA

Hi friends

i have the following questions. Thanks in advance for answering.

1. How PT calculates setup and hold time between 2 FF clocked by two different clocks?
2. When we use set_max_delay and set_min_delay , the delay calculated by the PT is over ridden, so what will happen to the data path( like will PT add “buf” to it)? How PT ensures the time will not exceeds the limit set using the above commands?
3. Calculate Min clock frequency at which the circuit can function?


Regards
Bdu

1> Launch at clock x and capture at next consequent edge of clock y. This needs analysis from design perspective since this can lead to data overwrite. So sometimes (most times ) we need a multi cycle path here.
2> PT will time the design, by default it will not buffer or optimize the path . If the path is violating the values, it'll show as violation.
You need to do a fix eco and generate the changes.

 

[vlsicute]

Re: doubt related to STA

Hi All,
Basically setup relationship will be defined for two different clocks with no relationship will be like below


Both clocks will be expanded to LCM of their time periods, most restrictive gap between will be taken as for setup computation. This relationship is very clear PT document
Message for this will be PTE-016 or PT-060.

CDC will be come into picture when relationship between them is declared as set_false_path. This should be verified by CDC tools and not by STA tools


Timing paths will be defined be like this
False path: Clocks are not related to each other and infinite interval between them. PT will stop checking timing relationship between the clocks.

 

[xavi]

Re: doubt related to STA



setup:
PrimeTime assumes that the corresponding launch edge is the nearest source clock edge occurring before the capture edge

hold:
The data launched by the setup launch edge must not be captured by the previous capture edge.
The data launched by the next launch edge must not be captured by the setup capture edge.