How PLDA encrypted his VHDL codes?

[Port Map]

Hi.
I saw some encrypted commercial VHDL codes of PLDA for PCIe.
It was interesting to me that how this codes were encrypted.
when I open the files like "pcie_ezdma_xilinx_full.vhd" nothing is readable in ASCII format.

Now, how can we create codes like this? is it possible.
(I'm familiar with encrypting the design by creating NGC file)

 

[FvM]

I guess, they are using an encryption feature of the Xilinx tools, also used with protected Xilinx IP.

 

[Port Map]

I think this is true. bu is there any more information?

 

[mrflibble]

Ask the vendor of that PCIe core?

 

[TrickyDicky]

NGC isnt encryption, its obfuscation.

 

[FvM]

NGC isnt encryption, its obfuscation.

Yes, but I suppose, the problem hasn't to do with NGC.

I'm not familiar with Xilinx ISE details. I presume they are using (more or less) strong cryptography for the IP sources and individual keys for licensed software packages. That's at least the way Altera handles protected IP, their own products as well as third party supplied (e.g. from PLDA). Optionally some IPs allow time-limited usage with the general tool license.