How much de-coupling capacitors needed?

[tony_lth]

Hi, Gurus,
For the power supply source, which is +12V, ripple is 30mV, and the cable length is 20cm. The load current is 4A.
Now I need to design the decoupling capacitors for the both ends of the cable,
So how much decoupling capacitors should I place?
Is 3pcs 330uF enough or not?

And how to avoid the resonance of my LC filter and the cable and the decoupling capacitors?

Best,
Tony Liu

 

[KlausST]

Hi,

impossible to answer.
It depends on a lot of things.
For example... If 4A is ohmic DC load then theoretically you don´t need a capacitor at all, because a capacitor only works for AC. For pure DC it is useless.

it dpends on the variation in current of the load and the speed of variation.
And it dpends on the regualtion speed of your supply.

Klaus

 

[andre_luis]

So how much decoupling capacitors should I place?
Is 3pcs 330uF enough or not?

Depending on the load, and how sensitive it is, In general another type capacitor must be placed in parallel close to these electrolitics in order to give to the power bus a better abitity to deliver instantaneous charges with smaller voltage drops; ceramics for instance have low intrinsic inductance and capacitances, and most often is spread on the board aswell.

 

[d123]

Hi,

This might be interesting, at least to have a look and read if not do the graphs it suggests:
Understanding Power Impedance Supply for Optimum Decoupling - Calex

I found it very helpful.

This is a good decoupling example with some nice, comprehensible formulas that can be applied to more circuit sections than just decoupling the specific IC in the app note. I feel it answers some of your questions and expands upon Klaus' honest answer - (sic) 'maybe, it depends':
OMAP5910 Decoupling/Filtering Techniques

 

[dick_freebird]

At the far end, assume the source is inductive and
constant current in effect.

Declare an acceptable far-end load sag voltage,
for a declared step-load pulse. Figure the coulombs
taken by that pulse over its duration, above the base
load current.

Your delta-V is capacitor-bank ((ESR*I)+(Q/C)). Your
two capacitor-related terms are ESR and C (I neglect
ESL, you may choose not to).

If it were me, I'd set it up in SPICE so you can play with
values and attributes.

 

[danadakk]

Capacitor technologies have varying ESR over frequency.

Regards, Dana.

 

[tony_lth]

@dick_freebird,
I am interesting your solution.
And I tried to simplified your method.
Say I placed 10cs 330uF(300mOhm), and DC current is about 2A@12V, so delta V1=0.3/10*2=60mV.

And for the 2nd step, it seems a little complex. Say my load is a FPGA, it consump 5V/2~3A, the current may vary 1A in 1 second. so its delta I=1A@5V. Then due to DCDC, delta I=0.41A@12V. So delta V2=0.41*1ohm=0.41V. Here 1ohm=5V*2.5Avg Cuurent/12V.

I don't know how to calculate Q/C, could any Guru comment?

Best,
Tony Liu