How much ADC sampling frequency be chosen for 30MHz IF (bandwidth = 5MHz)

[seema123]

Hello Friends,

I want my 30MHz IF to get sampled using the high speed 16-bit ADC. I am having one TI ADC having sampling rate of 250MSPS.

Should I do the oversampling my signal with 250MSPS sampling rate?
What will be its consequences & merits as well??

Looking forward for your kind suggestions!!
Regards
SV

 

[D.A.(Tony)Stewart]

Depending on Noise characteristics ....Roughly, when you increase the bandwidth "unnecessarily" for the signal of interest you get an extra bit of sampling resolution, for 2x to 4x over sample once filtering is applied.

 

[FvM]

There's no principle reason to use oversampling in this case, depending on the IF filter stop band attenuation you could even use pass band sampling (undersampling). On the other hand you can trade-off sampling rate against amplitude resolution using oversampling with respective decimation filters.

State-of-the-art digital receivers would probably use I/Q quadrature sampling.

 

[seema123]

Hi !!
Thanks friends for replying..

Why I am preferring 'oversampling' because I can get the processing gain and improvement in SNR. The prime criteria of my design is high SNR, SFDR, Wide dynamic range.

See I am having the choices of ADC sampling rate to be set at 80MSPS(LTC2216)/105MSPS/250MSPS(TI ADS42LB69IRGCT). What do you think of going ahead with 105MSPS (LTC2217)? And also since the final output desired is I/Q, so please suggest that out of the following which will be better:

(i) Using a single ADC for sampling the IF of 30MHz (with 4-5MHz BW)
(ii) Splitting the IF into two i.e. I & Q and then doing sampling both I & Q independently.


And also see that the sampled signal from ADC i am planning to fed to the latest FPGA device which will contain DDS (NCO based), Programmable Decimation CIC,CFIR & PFIR filtering stages. The final output from the FPGA board required is I/Q.

Regards
SV