how modify Traffic generator using MIG

[hannachifaten]

Hi every body ,
i try to use the MIG to Write and Read from DDR3 , i want to communicate my spartn 6 to DDR3 , i have used core generator Memory Interface Genrator( it generate output files in User Design and Example Design ), i choose begin with the example design using the traffic generator BUT :???: my worries are how to modify the Traffic genrator's file ( test bench ...) to write and read my own words ,
- i have done the first step that i'm tring to change the data_Mode to fixed mode , and i put only one word into " fixed_data_input"
after that i don't know how i can modify this last one to read and write different DATA , Don't forget i'm a begnner in VHDL and FPGA , i'm trainee :sad:

ANY HELP PLEASE ? :???:

 

[syedshan]

I suggest do not modify the code. It will be really tedious task.
Do you design. It will take much time, but this is the only way you can communicate through it.

 

[hannachifaten]

ok , i change this method , so i remove all the files of traffic genrator and i write my own user interface in the mem.tb.vhd such as a state machine , but that usually make errors

 

[syedshan]

of course that make errors but thats what learning is about. Just try and then people are here to help you.
what is mem.tb.vhd?
You need one module for signal generation, the other for synchornization with the MIG (i.e. making a sort of bridge to make signals compatible to the MIG). There will be combination of several modules...

 

[hannachifaten]

of course that make errors but thats what learning is about. Just try and then people are here to help you.
what is mem.tb.vhd?
You need one module for signal generation, the other for synchornization with the MIG (i.e. making a sort of bridge to make signals compatible to the MIG). There will be combination of several modules...

yes this module is the generation of signal( stimulus module without the traffic generator) which i replace the TRaffic Generator with state machine ,
i show you the port of this block :
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
--C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff"
--C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
--C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(

clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;


p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;

p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_wr_empty_i : in std_logic;


p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);


--vio_modify_enable : in std_logic;
--vio_data_mode_value : in std_logic_vector(2 downto 0);
--vio_addr_mode_value : in std_logic_vector(2 downto 0);

cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic
--error_status : out std_logic_vector(127 downto 0)


);
end memc3_tb_top;

after that i add a state machine


when i simulate the Example design after modification i usually have this error : Formal <p0_mcb_wr_empty_i> has no actual or default value.
:-|

Any suggestion :???:

 

[syedshan]

Hi

please use code tag so that your code is much clearer and easy to read and understand. This error usually occurs when you have some input pin left unconnected during instantiation.
Check for your top level model where a proper connecttion should be done for the said pin

 

[hannachifaten]

  --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
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-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
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-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor             : Xilinx
-- \   \   \/     Version            : 3.8
--  \   \         Application        : MIG
--  /   /         Filename           : memc3_tb_top.vhd
-- /___/   /\     Date Last Modified : $Date: 2011/05/27 15:50:35 $
-- \   \  /  \    Date Created       : Jul 03 2009
--  \___\/\___\
--
--Device           : Spartan-6
--Design Name      : DDR/DDR2/DDR3/LPDDR
--Purpose          : This is top level module for test bench. which instantiates 
--                   init_mem_pattern_ctr and mcb_traffic_gen modules for each user
--                   port.
--Reference        :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity memc3_tb_top is
generic
  (
      C_P0_MASK_SIZE                   : integer := 4;
      C_P0_DATA_PORT_SIZE              : integer := 32;
      C_P1_MASK_SIZE                   : integer := 4;
      C_P1_DATA_PORT_SIZE              : integer := 32;
      C_MEM_BURST_LEN                  : integer := 8;
      C_SIMULATION                     : string  := "FALSE";
      C_MEM_NUM_COL_BITS               : integer := 11;
      C_NUM_DQ_PINS                    : integer := 8;
      C_SMALL_DEVICE                   : string := "FALSE";
            C_p0_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000100";
      --C_p0_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
      C_p0_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000002ff"
      --C_p0_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffffc00";
      --C_p0_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000100"
  );
port
(

   clk0            : in std_logic;
   rst0            : in std_logic;
   calib_done      : in std_logic;


      p0_mcb_cmd_en_o                           : out std_logic;
      p0_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
      p0_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
      p0_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
      p0_mcb_cmd_full_i                         : in std_logic;

      p0_mcb_wr_en_o                            : out std_logic;
      p0_mcb_wr_mask_o                          : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
      p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
      p0_mcb_wr_full_i                          : in std_logic;
      p0_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
	   p0_mcb_wr_empty_i                         : in std_logic;


      p0_mcb_rd_en_o                            : out std_logic;
      p0_mcb_rd_data_i                          : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
      p0_mcb_rd_empty_i                         : in std_logic;
      p0_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);





   --vio_modify_enable   : in std_logic;
   --vio_data_mode_value : in std_logic_vector(2 downto 0);
   --vio_addr_mode_value : in std_logic_vector(2 downto 0);

   cmp_error       : out std_logic;
   cmp_data        : out std_logic_vector(31 downto 0);
   cmp_data_valid  : out std_logic;
   error           : out std_logic
   --error_status    : out std_logic_vector(127 downto 0)


);
end memc3_tb_top;

architecture arc of memc3_tb_top is

type state_type is (
                    WAIT_FOR_CALIB_DONE,  
                    WRITE_TO_FIFO_WORD1,  
                    WRITE_TO_FIFO_WORD2,  
                    WRITE_TO_FIFO_WORD3,  
                    WRITE_TO_FIFO_WORD4,  
                    CHECK_WRITE_READINESS,
                    ISSUE_WRITE_COMMAND,  
                    WAIT_FOR_WRITE,       
                    CHECK_READ_READINESS, 
                    ISSUE_READ_COMMAND,   
                    WAIT_FOR_READ,        
                    READ_FROM_FIFO_WORD1, 
                    READ_FROM_FIFO_WORD2, 
                    READ_FROM_FIFO_WORD3, 
                    READ_FROM_FIFO_WORD4, 
                    CLEAR_READ           
                    ); 
                    
signal state, next_state : state_type; 

--Declare internal signals for all outputs of the state-machine
signal cmp_error_r               : std_logic;
signal cmp_data_r                : std_logic_vector(31 downto 0);  
signal cmp_data_valid_r          : std_logic;  
signal p0_mcb_cmd_en_o_r         : std_logic;
signal p0_mcb_cmd_instr_o_r      : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_r         : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_r       : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_r          : std_logic;
signal p0_mcb_wr_mask_o_r        : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal p0_mcb_wr_data_o_r        : std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
signal p0_mcb_rd_en_o_r          : std_logic;

--MCB Instructions
   constant SIMPLE_WRITE              : std_logic_vector(2 downto 0)  := B"000";
   constant SIMPLE_READ               : std_logic_vector(2 downto 0)  := B"001";
   constant WRITE_WITH_AUTO_PRECHARGE : std_logic_vector(2 downto 0)  := B"010";
   constant READ_WITH_AUTO_PRECHARGE  : std_logic_vector(2 downto 0)  := B"011";
   constant REFRESH                   : std_logic_vector(2 downto 0)  := B"111";

begin

cmp_error          <= cmp_error_r;             
cmp_data           <= cmp_data_r(31 downto 0);
cmp_data_valid     <= cmp_data_valid_r;
p0_mcb_cmd_en_o    <= p0_mcb_cmd_en_o_r;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_r;
p0_mcb_cmd_bl_o    <= p0_mcb_cmd_bl_o_r;
p0_mcb_cmd_addr_o  <= p0_mcb_cmd_addr_o_r;
p0_mcb_wr_en_o     <= p0_mcb_wr_en_o_r;
p0_mcb_wr_mask_o   <= p0_mcb_wr_mask_o_r(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o   <= p0_mcb_wr_data_o_r(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_en_o     <= p0_mcb_rd_en_o_r;           

process (clk0)
begin  
   if (clk0'event and clk0 = '1') then
      if rst0 = '1' or calib_done = '0' then
         error <= '0';
      else
         -- latch the first error only
         if cmp_error_r = '1' then
            error <= '1';
         end if;
      end if;
   end if;
end process;

   SYNC_PROC: process (clk0)
   begin
      if (clk0'event and clk0 = '1') then
         if (rst0 = '1') then
            state <= WAIT_FOR_CALIB_DONE;
            cmp_error_r           <= '0';
            cmp_data_r            <= (others => '0');
            cmp_data_valid_r      <= '0';
            p0_mcb_cmd_en_o_r     <= '0';
            p0_mcb_cmd_instr_o_r  <= (others => '0');
            p0_mcb_cmd_bl_o_r     <= (others => '0');
            p0_mcb_cmd_addr_o_r   <= (others => '0');
            p0_mcb_wr_en_o_r      <= '0';
            p0_mcb_wr_mask_o_r    <= (others => '0');
            p0_mcb_wr_data_o_r    <= (others => '0');
            p0_mcb_rd_en_o_r      <= '0';
         else                 
            case (state) is
               when WAIT_FOR_CALIB_DONE =>
                   if calib_done = '1' AND p0_mcb_wr_empty_i = '1'  then
                      state <= WRITE_TO_FIFO_WORD1;
                   else
                      state <= WAIT_FOR_CALIB_DONE;
                   end if;
               when WRITE_TO_FIFO_WORD1 =>
                   state                <= WRITE_TO_FIFO_WORD2;
                   p0_mcb_wr_data_o_r   <= X"12345678";
                   p0_mcb_wr_en_o_r     <= '1';
                   p0_mcb_wr_mask_o_r   <= B"0000";
               when WRITE_TO_FIFO_WORD2 => 
                   state                <= WRITE_TO_FIFO_WORD3;
                   p0_mcb_wr_data_o_r   <= X"AAAAAAAA";
                   p0_mcb_wr_en_o_r     <= '1';
                   p0_mcb_wr_mask_o_r   <= B"0000";
               when WRITE_TO_FIFO_WORD3 => 
                   state                <= WRITE_TO_FIFO_WORD4;
                   p0_mcb_wr_data_o_r   <= X"55555555";
                   p0_mcb_wr_en_o_r     <= '1';
                   p0_mcb_wr_mask_o_r   <= B"0000";
               when WRITE_TO_FIFO_WORD4 => 
                   if p0_mcb_cmd_full_i = '0' then
                      state <= ISSUE_WRITE_COMMAND;
                   else
                      state <= CHECK_WRITE_READINESS;
                   end if;
                   p0_mcb_wr_data_o_r   <= X"DEADBEEF";
                   p0_mcb_wr_en_o_r     <= '1';
                   p0_mcb_wr_mask_o_r   <= B"0000";
               when CHECK_WRITE_READINESS => 
                   if p0_mcb_cmd_full_i = '0' then
                      state <= ISSUE_WRITE_COMMAND;
                   else
                      state <= CHECK_WRITE_READINESS;
                   end if;
                   p0_mcb_wr_data_o_r   <= (others => '0');
                   p0_mcb_wr_en_o_r     <= '0';
                   p0_mcb_wr_mask_o_r   <= B"0000";
               when ISSUE_WRITE_COMMAND => 
                   state                <= WAIT_FOR_WRITE;
                   p0_mcb_wr_data_o_r   <= (others => '0');
                   p0_mcb_wr_en_o_r     <= '0';
                   p0_mcb_wr_mask_o_r   <= B"0000";
                   p0_mcb_cmd_bl_o_r    <= B"000011";     -- burst length of 3 bursts 4
                   p0_mcb_cmd_addr_o_r  <= (others => '0');
                   p0_mcb_cmd_instr_o_r <= SIMPLE_WRITE;
                   p0_mcb_cmd_en_o_r    <= '1';
               when WAIT_FOR_WRITE => 
                   if p0_mcb_wr_empty_i = '1' then
                      state <= CHECK_READ_READINESS;
                   else
                      state <= WAIT_FOR_WRITE;
                   end if;
                   p0_mcb_cmd_bl_o_r    <= (others => '0');
                   p0_mcb_cmd_addr_o_r  <= (others => '0');
                   p0_mcb_cmd_instr_o_r <= (others => '0');
                   p0_mcb_cmd_en_o_r    <= '0';
               when CHECK_READ_READINESS =>
                   if p0_mcb_cmd_full_i = '0' then
                      state <= ISSUE_READ_COMMAND;
                   else
                      state <= CHECK_READ_READINESS;
                   end if;
               when ISSUE_READ_COMMAND => 
                   state                <= WAIT_FOR_READ;
                   p0_mcb_cmd_bl_o_r    <= B"000011";     -- burst length of 3 bursts 4
                   p0_mcb_cmd_addr_o_r  <= (others => '0');
                   p0_mcb_cmd_instr_o_r <= SIMPLE_READ;
                   p0_mcb_cmd_en_o_r    <= '1';
               when WAIT_FOR_READ => 
                   if p0_mcb_rd_empty_i = '0' then
                      state <= READ_FROM_FIFO_WORD1;
                   else
                      state <= WAIT_FOR_READ;
                   end if;
                   p0_mcb_cmd_bl_o_r    <= (others => '0');
                   p0_mcb_cmd_addr_o_r  <= (others => '0');
                   p0_mcb_cmd_instr_o_r <= (others => '0');
                   p0_mcb_cmd_en_o_r    <= '0';
                   cmp_data_r           <= X"12345678";
               when READ_FROM_FIFO_WORD1 => 
                   state                <= READ_FROM_FIFO_WORD2;
                   p0_mcb_rd_en_o_r     <= '1';
                   cmp_data_r           <= X"12345678";
                   cmp_data_valid_r     <= '1';
                   if cmp_data_r = p0_mcb_rd_data_i then
                      cmp_error_r <= '0';
                   else
                      cmp_error_r <= '1';
                   end if;
               when READ_FROM_FIFO_WORD2 => 
                   state                <= READ_FROM_FIFO_WORD3;
                   p0_mcb_rd_en_o_r     <= '1';
                   cmp_data_r           <= X"AAAAAAAA";
                   cmp_data_valid_r     <= '1';
                   if cmp_data_r = p0_mcb_rd_data_i then
                      cmp_error_r <= '0';
                   else
                      cmp_error_r <= '1';
                   end if;
               when READ_FROM_FIFO_WORD3 => 
                   state                <= READ_FROM_FIFO_WORD4;
                   p0_mcb_rd_en_o_r     <= '1';
                   cmp_data_r           <= X"55555555";
                   cmp_data_valid_r     <= '1';
                   if cmp_data_r = p0_mcb_rd_data_i then
                      cmp_error_r <= '0';
                   else
                      cmp_error_r <= '1';
                   end if;
               when READ_FROM_FIFO_WORD4 => 
                   state                <= CLEAR_READ;
                   p0_mcb_rd_en_o_r     <= '1';
                   cmp_data_r           <= X"DEADBEEF";
                   cmp_data_valid_r     <= '1';
                   if cmp_data_r = p0_mcb_rd_data_i then
                      cmp_error_r <= '0';
                   else
                      cmp_error_r <= '1';
                   end if;
               when CLEAR_READ => 
                   if calib_done = '1' AND p0_mcb_wr_empty_i = '1' then
                      state <= WRITE_TO_FIFO_WORD1;
                   else
                      state <= WAIT_FOR_CALIB_DONE;
                   end if;
                   p0_mcb_rd_en_o_r     <= '0';
                   cmp_data_r           <= (others => '0');
                   cmp_data_valid_r     <= '0';
                   cmp_error_r          <= '0';
               when others =>
                  state <= WAIT_FOR_CALIB_DONE;
            end case;      
         end if;        
      end if;
   end process;
 
end architecture;

like this you mean ? because i can not attached any file from this laptom :-(

 

[TrickyDicky]

when i simulate the Example design after modification i usually have this error : Formal <p0_mcb_wr_empty_i> has no actual or default value.
:-|

Any suggestion :???:

That means you havent connected it in your testbench or design example. All inputs without a default value, which would look like this:

p0_mcb_wr_empty_i : in std_logic := '0'; -- connect to '0' if not connected above

Must have a value assigned to them in their port map.

 

[hannachifaten]

That means you havent connected it in your testbench or design example. All inputs without a default value, which would look like this:

p0_mcb_wr_empty_i : in std_logic := '0'; -- connect to '0' if not connected above

Must have a value assigned to them in their port map.

Thanks that's help me a lot TrickyDicky , now i try to define an input but it will be variable not constant , so
i try to add an input V in entity and i define this like a signal OR constant i want to change this lines :
whenever i give a value to V
so i define V like this in entity :

Va : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);

in architecture i don't know if i define as signal or constant :

constant Va : std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) := X"1156666";

signal Va : std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) := X"12345678";

p0_mcb_wr_data_o_r <= X"12345678"; become like this :

p0_mcb_wr_data_o_r <= Va ;

But this make me errors :-|

any reply please

 

[TrickyDicky]

where are you instantiating this memc3_tb_top? what are you actually trying to do? is this a simulation - are you just trying to simulate memc3_tb_top on its own? you will need some form of testbench to simulate it.

I dont really understand what you're talking about in yoiur post... please post some code.

 

[hannachifaten]

where are you instantiating this memc3_tb_top? what are you actually trying to do? is this a simulation - are you just trying to simulate memc3_tb_top on its own? you will need some form of testbench to simulate it.

I dont really understand what you're talking about in yoiur post... please post some code.

now i try to simulate i want to change my data :
in the previous programm i used a fixed data X"12345678" i simulate this data with a test bench file ,
i want to replace this data with an other which be variable

when WRITE_TO_FIFO_WORD1 =>
                   state                <= WRITE_TO_FIFO_WORD2;
                   --p0_mcb_wr_data_o_r   <= X"12345678";                            this is fixed data   
		p0_mcb_wr_data_o_r   <= Va;                          I want to change my Data Va ( variable data ) 
                   p0_mcb_wr_en_o_r     <= '1';
                   p0_mcb_wr_mask_o_r   <= B"0000";

So i tried to add an inoutput like this :

port
(

   clk0            : in std_logic;
   rst0            : in std_logic;
   calib_done      : in std_logic;
   Va              : inout std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);

after that I dont know if i define my Va as an internal signal or constant in my testbench file

  signal         Va                        : std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) := X"12345678";
            constant    Va                        : std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) := X"12345678";

i hope that you inderstand me :sad:

 

[TrickyDicky]

I still dont understand - please post the file that instantiates memc3_tb_top.

 

[hannachifaten]

--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor             : Xilinx
-- \   \   \/     Version            : 3.7
--  \   \         Application        : MIG
--  /   /         Filename           : example_top.vhd
-- /___/   /\     Date Last Modified : $Date: 2010/10/05 16:42:51 $
-- \   \  /  \    Date Created       : Jul 03 2009
--  \___\/\___\
--
--Device           : Spartan-6
--Design Name      : DDR/DDR2/DDR3/LPDDR 
--Purpose          : This is the design top level. which instantiates top wrapper,
--                   test bench top and infrastructure modules.
--Reference        :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
  (
            C3_P0_MASK_SIZE           : integer := 4;
          C3_P0_DATA_PORT_SIZE      : integer := 32;
          C3_P1_MASK_SIZE           : integer := 4;
          C3_P1_DATA_PORT_SIZE      : integer := 32;
    C3_MEMCLK_PERIOD        : integer := 5000; 
                                       -- Memory data transfer clock period.
    C3_RST_ACT_LOW          : integer := 0; 
                                       -- # = 1 for active low reset,
                                       -- # = 0 for active high reset.
    C3_INPUT_CLK_TYPE       : string := "SINGLE_ENDED"; 
                                       -- input clock type DIFFERENTIAL or SINGLE_ENDED.
    C3_CALIB_SOFT_IP        : string := "TRUE"; 
                                       -- # = TRUE, Enables the soft calibration logic,
                                       -- # = FALSE, Disables the soft calibration logic.
    C3_SIMULATION           : string := "FALSE"; 
                                       -- # = TRUE, Simulating the design. Useful to reduce the simulation time,
                                       -- # = FALSE, Implementing the design.
-- avt    C3_HW_TESTING           : string := "FALSE"; 
    C3_HW_TESTING           : string := "TRUE"; 
                                       -- Determines the address space accessed by the traffic generator,
                                       -- # = FALSE, Smaller address space,
                                       -- # = TRUE, Large address space.
    DEBUG_EN                : integer := 1; 
                                       -- # = 1, Enable debug signals/controls,
                                       --   = 0, Disable debug signals/controls.
    C3_MEM_ADDR_ORDER       : string := "ROW_BANK_COLUMN"; 
                                       -- The order in which user address is provided to the memory controller,
                                       -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
    C3_NUM_DQ_PINS          : integer := 16; 
                                       -- External memory data width.
    C3_MEM_ADDR_WIDTH       : integer := 13; 
                                       -- External memory address width.
    C3_MEM_BANKADDR_WIDTH   : integer := 2 
                                       -- External memory bank address width.
  );
   
  port
  (
   calib_done                              : out std_logic;
   error                                   : out std_logic;
   mcb3_dram_dq                            : inout  std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
   mcb3_dram_a                             : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
   mcb3_dram_ba                            : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
   mcb3_dram_cke                           : out std_logic;
   mcb3_dram_ras_n                         : out std_logic;
   mcb3_dram_cas_n                         : out std_logic;
   mcb3_dram_we_n                          : out std_logic;
   mcb3_dram_dm                            : out std_logic;
   mcb3_dram_udqs                          : inout  std_logic;
   mcb3_rzq                                : inout  std_logic;
   mcb3_dram_udm                           : out std_logic;
   c3_sys_clk                              : in  std_logic;
   c3_sys_rst_n                            : in  std_logic;
   mcb3_dram_dqs                           : inout  std_logic;
   mcb3_dram_ck                            : out std_logic;
   mcb3_dram_ck_n                          : out std_logic ;
	[B]Va                                      :in std_logic_vector(31 downto 0):= X"11110000"[/B]  //  i dont know if i must declared this here or not // 
  );
end example_top;

architecture arc of example_top is

 

component icon
    port (
      CONTROL0 : inout std_logic_vector(35 downto 0);
      CONTROL1 : inout std_logic_vector(35 downto 0)
      );
  end component;

  component ila
    port (
     CLK     : in    std_logic;
     DATA    : in    std_logic_vector(255 downto 0);
     TRIG0   : in    std_logic_vector(1 downto 0);
     CONTROL : inout std_logic_vector(35 downto 0)
     );
  end component;

  component vio
    port (
      CONTROL : inout std_logic_vector(35 downto 0);
      ASYNC_OUT: out std_logic_vector(6 downto 0)
      );
  end component;

  attribute syn_black_box          : boolean;
  attribute syn_noprune            : boolean;
  attribute syn_black_box of icon  : component is TRUE;
  attribute syn_noprune of icon    : component is TRUE;
  attribute syn_black_box of ila   : component is TRUE;
  attribute syn_noprune of ila     : component is TRUE;
  attribute syn_black_box of vio   : component is TRUE;
  attribute syn_noprune of vio     : component is TRUE;

	

component memc3_infrastructure is
    generic (
      C_RST_ACT_LOW        : integer;
      C_INPUT_CLK_TYPE     : string;
      C_CLKOUT0_DIVIDE     : integer;
      C_CLKOUT1_DIVIDE     : integer;
      C_CLKOUT2_DIVIDE     : integer;
      C_CLKOUT3_DIVIDE     : integer;
      C_CLKFBOUT_MULT      : integer;
      C_DIVCLK_DIVIDE      : integer;
      C_INCLK_PERIOD       : integer

      );
    port (
      sys_clk_p                              : in    std_logic;
      sys_clk_n                              : in    std_logic;
      sys_clk                                : in    std_logic;
      sys_rst_n                              : in    std_logic;
      clk0                                   : out   std_logic;
      rst0                                   : out   std_logic;
      async_rst                              : out   std_logic;
      sysclk_2x                              : out   std_logic;
      sysclk_2x_180                          : out   std_logic;
      pll_ce_0                               : out   std_logic;
      pll_ce_90                              : out   std_logic;
      pll_lock                               : out   std_logic;
      mcb_drp_clk                            : out   std_logic

      );
  end component;


component memc3_wrapper is
    generic (
      C_MEMCLK_PERIOD      : integer;
      C_CALIB_SOFT_IP      : string;
      C_SIMULATION         : string;
      C_P0_MASK_SIZE       : integer;
      C_P0_DATA_PORT_SIZE   : integer;
      C_P1_MASK_SIZE       : integer;
      C_P1_DATA_PORT_SIZE   : integer;
      C_ARB_NUM_TIME_SLOTS   : integer;
      C_ARB_TIME_SLOT_0    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_1    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_2    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_3    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_4    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_5    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_6    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_7    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_8    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_9    : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_10   : bit_vector(2 downto 0);
      C_ARB_TIME_SLOT_11   : bit_vector(2 downto 0);
      C_MEM_TRAS           : integer;
      C_MEM_TRCD           : integer;
      C_MEM_TREFI          : integer;
      C_MEM_TRFC           : integer;
      C_MEM_TRP            : integer;
      C_MEM_TWR            : integer;
      C_MEM_TRTP           : integer;
      C_MEM_TWTR           : integer;
      C_MEM_ADDR_ORDER     : string;
      C_NUM_DQ_PINS        : integer;
      C_MEM_TYPE           : string;
      C_MEM_DENSITY        : string;
      C_MEM_BURST_LEN      : integer;
      C_MEM_CAS_LATENCY    : integer;
      C_MEM_ADDR_WIDTH     : integer;
      C_MEM_BANKADDR_WIDTH   : integer;
      C_MEM_NUM_COL_BITS   : integer;
      C_MEM_DDR1_2_ODS     : string;
      C_MEM_DDR2_RTT       : string;
      C_MEM_DDR2_DIFF_DQS_EN   : string;
      C_MEM_DDR2_3_PA_SR   : string;
      C_MEM_DDR2_3_HIGH_TEMP_SR   : string;
      C_MEM_DDR3_CAS_LATENCY   : integer;
      C_MEM_DDR3_ODS       : string;
      C_MEM_DDR3_RTT       : string;
      C_MEM_DDR3_CAS_WR_LATENCY   : integer;
      C_MEM_DDR3_AUTO_SR   : string;
      C_MEM_DDR3_DYN_WRT_ODT   : string;
      C_MEM_MOBILE_PA_SR   : string;
      C_MEM_MDDR_ODS       : string;
      C_MC_CALIB_BYPASS    : string;
      C_MC_CALIBRATION_MODE   : string;
      C_MC_CALIBRATION_DELAY   : string;
      C_SKIP_IN_TERM_CAL   : integer;
      C_SKIP_DYNAMIC_CAL   : integer;
      C_LDQSP_TAP_DELAY_VAL   : integer;
      C_LDQSN_TAP_DELAY_VAL   : integer;
      C_UDQSP_TAP_DELAY_VAL   : integer;
      C_UDQSN_TAP_DELAY_VAL   : integer;
      C_DQ0_TAP_DELAY_VAL   : integer;
      C_DQ1_TAP_DELAY_VAL   : integer;
      C_DQ2_TAP_DELAY_VAL   : integer;
      C_DQ3_TAP_DELAY_VAL   : integer;
      C_DQ4_TAP_DELAY_VAL   : integer;
      C_DQ5_TAP_DELAY_VAL   : integer;
      C_DQ6_TAP_DELAY_VAL   : integer;
      C_DQ7_TAP_DELAY_VAL   : integer;
      C_DQ8_TAP_DELAY_VAL   : integer;
      C_DQ9_TAP_DELAY_VAL   : integer;
      C_DQ10_TAP_DELAY_VAL   : integer;
      C_DQ11_TAP_DELAY_VAL   : integer;
      C_DQ12_TAP_DELAY_VAL   : integer;
      C_DQ13_TAP_DELAY_VAL   : integer;
      C_DQ14_TAP_DELAY_VAL   : integer;
      C_DQ15_TAP_DELAY_VAL   : integer
      );
    port (
      mcb3_dram_dq                           : inout  std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
      mcb3_dram_a                            : out  std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
      mcb3_dram_ba                           : out  std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
      mcb3_dram_cke                          : out  std_logic;
      mcb3_dram_ras_n                        : out  std_logic;
      mcb3_dram_cas_n                        : out  std_logic;
      mcb3_dram_we_n                         : out  std_logic;
      mcb3_dram_dm                           : out  std_logic;
      mcb3_dram_udqs                         : inout  std_logic;
      mcb3_rzq                               : inout  std_logic;
      mcb3_dram_udm                          : out  std_logic;
      calib_done                             : out  std_logic;
      async_rst                              : in  std_logic;
      sysclk_2x                              : in  std_logic;
      sysclk_2x_180                          : in  std_logic;
      pll_ce_0                               : in  std_logic;
      pll_ce_90                              : in  std_logic;
      pll_lock                               : in  std_logic;
      mcb_drp_clk                            : in  std_logic;
      mcb3_dram_dqs                          : inout  std_logic;
      mcb3_dram_ck                           : out  std_logic;
      mcb3_dram_ck_n                         : out  std_logic;
      p0_cmd_clk                            : in std_logic;
      p0_cmd_en                             : in std_logic;
      p0_cmd_instr                          : in std_logic_vector(2 downto 0);
      p0_cmd_bl                             : in std_logic_vector(5 downto 0);
      p0_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
      p0_cmd_empty                          : out std_logic;
      p0_cmd_full                           : out std_logic;
      p0_wr_clk                             : in std_logic;
      p0_wr_en                              : in std_logic;
      p0_wr_mask                            : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
      p0_wr_data                            : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
      p0_wr_full                            : out std_logic;
      p0_wr_empty                           : out std_logic;
      p0_wr_count                           : out std_logic_vector(6 downto 0);
      p0_wr_underrun                        : out std_logic;
      p0_wr_error                           : out std_logic;
      p0_rd_clk                             : in std_logic;
      p0_rd_en                              : in std_logic;
      p0_rd_data                            : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
      p0_rd_full                            : out std_logic;
      p0_rd_empty                           : out std_logic;
      p0_rd_count                           : out std_logic_vector(6 downto 0);
      p0_rd_overflow                        : out std_logic;
      p0_rd_error                           : out std_logic;
      selfrefresh_enter                     : in std_logic;
      selfrefresh_mode                      : out std_logic

      );
  end component;


component memc3_tb_top is
    generic (
      C_SIMULATION         : string;
      C_P0_MASK_SIZE       : integer;
      C_P0_DATA_PORT_SIZE   : integer;
      C_NUM_DQ_PINS        : integer;
      C_MEM_BURST_LEN      : integer;
      C_MEM_NUM_COL_BITS   : integer;
      C_SMALL_DEVICE       : string;
      C_p0_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0); 
      C_p0_END_ADDRESS                        : std_logic_vector(31 downto 0)
      );
    port (
      error                                  : out   std_logic;
      calib_done                             : in    std_logic;
      clk0                                   : in    std_logic;
      rst0                                   : in    std_logic;
      cmp_error                              : out   std_logic;
      cmp_data_valid                         : out   std_logic;
      cmp_data                               : out  std_logic_vector(31 downto 0);
      p0_mcb_cmd_en_o                           : out std_logic;
      p0_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
      p0_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
      p0_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
      p0_mcb_cmd_full_i                         : in std_logic;
      p0_mcb_wr_en_o                            : out std_logic;
      p0_mcb_wr_mask_o                          : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
      p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
		--p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
      p0_mcb_wr_full_i                          : in std_logic;
      p0_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
      p0_mcb_wr_empty_i                         : in std_logic;
      p0_mcb_rd_en_o                            : out std_logic;
      p0_mcb_rd_data_i                          : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
      p0_mcb_rd_empty_i                         : in std_logic;
      p0_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0) ;  
      Va                                        : inout std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0)   [B]i add this line to change the input data [/B]
      );
  end component;



  function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) )  return  std_logic_vector is
   begin
   if (C3_HW_TESTING = "FALSE") then
     return val1;
   else
     return val2;
   end if;
   end function;



--avt   constant C3_CLKOUT0_DIVIDE       : integer := 2; 
--avt   constant C3_CLKOUT1_DIVIDE       : integer := 2; 
--avt   constant C3_CLKOUT2_DIVIDE       : integer := 16; 
--avt   constant C3_CLKOUT3_DIVIDE       : integer := 8; 
--avt   constant C3_CLKFBOUT_MULT        : integer := 4; 
   constant C3_CLKOUT0_DIVIDE       : integer := 1; 
   constant C3_CLKOUT1_DIVIDE       : integer := 1; 
   constant C3_CLKOUT2_DIVIDE       : integer := 8; 
   constant C3_CLKOUT3_DIVIDE       : integer := 8; 
   constant C3_CLKFBOUT_MULT        : integer := 6; 
   constant C3_DIVCLK_DIVIDE        : integer := 1; 
   constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); 
   constant C3_ARB_NUM_TIME_SLOTS   : integer := 12; 
   constant C3_ARB_TIME_SLOT_0      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_1      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_2      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_3      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_4      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_5      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_6      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_7      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_8      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_9      : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_10     : bit_vector(2 downto 0) := o"0"; 
   constant C3_ARB_TIME_SLOT_11     : bit_vector(2 downto 0) := o"0"; 
   constant C3_MEM_TRAS             : integer := 40000; 
   constant C3_MEM_TRCD             : integer := 15000; 
   constant C3_MEM_TREFI            : integer := 7800000; 
   constant C3_MEM_TRFC             : integer := 97500; 
   constant C3_MEM_TRP              : integer := 15000; 
   constant C3_MEM_TWR              : integer := 15000; 
   constant C3_MEM_TRTP             : integer := 7500; 
   constant C3_MEM_TWTR             : integer := 2; 
   constant C3_MEM_TYPE             : string := "MDDR"; 
   constant C3_MEM_DENSITY          : string := "512Mb"; 
   constant C3_MEM_BURST_LEN        : integer := 4; 
   constant C3_MEM_CAS_LATENCY      : integer := 3; 
   constant C3_MEM_NUM_COL_BITS     : integer := 10; 
   constant C3_MEM_DDR1_2_ODS       : string := "FULL"; 
   constant C3_MEM_DDR2_RTT         : string := "50OHMS"; 
   constant C3_MEM_DDR2_DIFF_DQS_EN  : string := "YES"; 
   constant C3_MEM_DDR2_3_PA_SR     : string := "FULL"; 
   constant C3_MEM_DDR2_3_HIGH_TEMP_SR  : string := "NORMAL"; 
   constant C3_MEM_DDR3_CAS_LATENCY  : integer := 6; 
   constant C3_MEM_DDR3_ODS         : string := "DIV6"; 
   constant C3_MEM_DDR3_RTT         : string := "DIV2"; 
   constant C3_MEM_DDR3_CAS_WR_LATENCY  : integer := 5; 
   constant C3_MEM_DDR3_AUTO_SR     : string := "ENABLED"; 
   constant C3_MEM_DDR3_DYN_WRT_ODT  : string := "OFF"; 
   constant C3_MEM_MOBILE_PA_SR     : string := "FULL"; 
   constant C3_MEM_MDDR_ODS         : string := "FULL"; 
   constant C3_MC_CALIB_BYPASS      : string := "NO"; 
   constant C3_MC_CALIBRATION_MODE  : string := "CALIBRATION"; 
   constant C3_MC_CALIBRATION_DELAY  : string := "HALF"; 
   constant C3_SKIP_IN_TERM_CAL     : integer := 1; 
   constant C3_SKIP_DYNAMIC_CAL     : integer := 0; 
   constant C3_LDQSP_TAP_DELAY_VAL  : integer := 0; 
   constant C3_LDQSN_TAP_DELAY_VAL  : integer := 0; 
   constant C3_UDQSP_TAP_DELAY_VAL  : integer := 0; 
   constant C3_UDQSN_TAP_DELAY_VAL  : integer := 0; 
   constant C3_DQ0_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ1_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ2_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ3_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ4_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ5_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ6_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ7_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ8_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ9_TAP_DELAY_VAL    : integer := 0; 
   constant C3_DQ10_TAP_DELAY_VAL   : integer := 0; 
   constant C3_DQ11_TAP_DELAY_VAL   : integer := 0; 
   constant C3_DQ12_TAP_DELAY_VAL   : integer := 0; 
   constant C3_DQ13_TAP_DELAY_VAL   : integer := 0; 
   constant C3_DQ14_TAP_DELAY_VAL   : integer := 0; 
   constant C3_DQ15_TAP_DELAY_VAL   : integer := 0; 
   constant C3_SMALL_DEVICE         : string := "TRUE"; 
   constant C3_p0_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000100", x"01000000");
   constant C3_p0_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
   constant C3_p0_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000002ff", x"02ffffff");
   constant C3_p0_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffffc00", x"fc000000");
   constant C3_p0_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000100", x"01000000");

  signal  c3_sys_clk_p                             : std_logic;
  signal  c3_sys_clk_n                             : std_logic;
  signal  c3_error                                 : std_logic;
  signal  c3_calib_done                            : std_logic;
  signal  c3_clk0                                  : std_logic;
  signal  c3_rst0                                  : std_logic;
  signal  c3_async_rst                             : std_logic;
  signal  c3_sysclk_2x                             : std_logic;
  signal  c3_sysclk_2x_180                         : std_logic;
  signal  c3_pll_ce_0                              : std_logic;
  signal  c3_pll_ce_90                             : std_logic;
  signal  c3_pll_lock                              : std_logic;
  signal  c3_mcb_drp_clk                           : std_logic;
  signal  c3_cmp_error                             : std_logic;
  signal  c3_cmp_data_valid                        : std_logic;
  signal  c3_vio_modify_enable                     : std_logic;
  signal  c3_vio_data_mode_value                   : std_logic_vector(2 downto 0);
  signal  c3_vio_addr_mode_value                   : std_logic_vector(2 downto 0);
  signal  c3_cmp_data                              : std_logic_vector(31 downto 0);
  signal  c3_p0_cmd_en                             : std_logic;
  signal  c3_p0_cmd_instr                          : std_logic_vector(2 downto 0);
  signal  c3_p0_cmd_bl                             : std_logic_vector(5 downto 0);
  signal  c3_p0_cmd_byte_addr                      : std_logic_vector(29 downto 0);
  signal  c3_p0_cmd_empty                          : std_logic;
  signal  c3_p0_cmd_full                           : std_logic;
  signal  c3_p0_wr_en                              : std_logic;
  signal  c3_p0_wr_mask                            : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
  signal  c3_p0_wr_data                            : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
  signal  c3_p0_wr_full                            : std_logic;
  signal  c3_p0_wr_empty                           : std_logic;
  signal  c3_p0_wr_count                           : std_logic_vector(6 downto 0);
  signal  c3_p0_wr_underrun                        : std_logic;
  signal  c3_p0_wr_error                           : std_logic;
  signal  c3_p0_rd_en                              : std_logic;
  signal  c3_p0_rd_data                            : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
  signal  c3_p0_rd_full                            : std_logic;
  signal  c3_p0_rd_empty                           : std_logic;
  signal  c3_p0_rd_count                           : std_logic_vector(6 downto 0);
  signal  c3_p0_rd_overflow                        : std_logic;
  signal  c3_p0_rd_error                           : std_logic;

  signal  c3_selfrefresh_enter                     : std_logic;
  signal  c3_selfrefresh_mode                      : std_logic;


	-- debug signals declarations
   signal c3_dbg_data : std_logic_vector(255 downto 0);
   signal c3_dbg_trig : std_logic_vector(1 downto 0);
   signal c3_control0 : std_logic_vector(35 downto 0);
   signal c3_control1 : std_logic_vector(35 downto 0);
   signal c3_vio_out : std_logic_vector(6 downto 0);
--avt   signal c3_zeroes1 : std_logic_vector(87 downto 0 ):= (others => '0');
	signal c3_zeroes1 : std_logic_vector(85 downto 0 ):= (others => '0');
   signal c3_zeroes2 : std_logic_vector(143 downto 0 ):= (others => '0');

	



begin
 error <= c3_error;
calib_done <= c3_calib_done;
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';

memc3_infrastructure_inst : memc3_infrastructure

generic map
 (
   C_RST_ACT_LOW                     => C3_RST_ACT_LOW,
   C_INPUT_CLK_TYPE                  => C3_INPUT_CLK_TYPE,
   C_CLKOUT0_DIVIDE                  => C3_CLKOUT0_DIVIDE,
   C_CLKOUT1_DIVIDE                  => C3_CLKOUT1_DIVIDE,
   C_CLKOUT2_DIVIDE                  => C3_CLKOUT2_DIVIDE,
   C_CLKOUT3_DIVIDE                  => C3_CLKOUT3_DIVIDE,
   C_CLKFBOUT_MULT                   => C3_CLKFBOUT_MULT,
   C_DIVCLK_DIVIDE                   => C3_DIVCLK_DIVIDE,
   C_INCLK_PERIOD                    => C3_INCLK_PERIOD
   )
port map
 (
   sys_clk_p                       => c3_sys_clk_p,
   sys_clk_n                       => c3_sys_clk_n,
   sys_clk                         => c3_sys_clk,
   sys_rst_n                       => c3_sys_rst_n,
   clk0                            => c3_clk0,
   rst0                            => c3_rst0,
   async_rst                       => c3_async_rst,
   sysclk_2x                       => c3_sysclk_2x,
   sysclk_2x_180                   => c3_sysclk_2x_180,
   pll_ce_0                        => c3_pll_ce_0,
   pll_ce_90                       => c3_pll_ce_90,
   pll_lock                        => c3_pll_lock,
   mcb_drp_clk                     => c3_mcb_drp_clk
   );


-- wrapper instantiation
 memc3_wrapper_inst : memc3_wrapper

generic map
 (
   C_MEMCLK_PERIOD                   => C3_MEMCLK_PERIOD,
   C_CALIB_SOFT_IP                   => C3_CALIB_SOFT_IP,
   C_SIMULATION                      => C3_SIMULATION,
   C_P0_MASK_SIZE                    => C3_P0_MASK_SIZE,
   C_P0_DATA_PORT_SIZE               => C3_P0_DATA_PORT_SIZE,
   C_P1_MASK_SIZE                    => C3_P1_MASK_SIZE,
   C_P1_DATA_PORT_SIZE               => C3_P1_DATA_PORT_SIZE,
   C_ARB_NUM_TIME_SLOTS              => C3_ARB_NUM_TIME_SLOTS,
   C_ARB_TIME_SLOT_0                 => C3_ARB_TIME_SLOT_0,
   C_ARB_TIME_SLOT_1                 => C3_ARB_TIME_SLOT_1,
   C_ARB_TIME_SLOT_2                 => C3_ARB_TIME_SLOT_2,
   C_ARB_TIME_SLOT_3                 => C3_ARB_TIME_SLOT_3,
   C_ARB_TIME_SLOT_4                 => C3_ARB_TIME_SLOT_4,
   C_ARB_TIME_SLOT_5                 => C3_ARB_TIME_SLOT_5,
   C_ARB_TIME_SLOT_6                 => C3_ARB_TIME_SLOT_6,
   C_ARB_TIME_SLOT_7                 => C3_ARB_TIME_SLOT_7,
   C_ARB_TIME_SLOT_8                 => C3_ARB_TIME_SLOT_8,
   C_ARB_TIME_SLOT_9                 => C3_ARB_TIME_SLOT_9,
   C_ARB_TIME_SLOT_10                => C3_ARB_TIME_SLOT_10,
   C_ARB_TIME_SLOT_11                => C3_ARB_TIME_SLOT_11,
   C_MEM_TRAS                        => C3_MEM_TRAS,
   C_MEM_TRCD                        => C3_MEM_TRCD,
   C_MEM_TREFI                       => C3_MEM_TREFI,
   C_MEM_TRFC                        => C3_MEM_TRFC,
   C_MEM_TRP                         => C3_MEM_TRP,
   C_MEM_TWR                         => C3_MEM_TWR,
   C_MEM_TRTP                        => C3_MEM_TRTP,
   C_MEM_TWTR                        => C3_MEM_TWTR,
   C_MEM_ADDR_ORDER                  => C3_MEM_ADDR_ORDER,
   C_NUM_DQ_PINS                     => C3_NUM_DQ_PINS,
   C_MEM_TYPE                        => C3_MEM_TYPE,
   C_MEM_DENSITY                     => C3_MEM_DENSITY,
   C_MEM_BURST_LEN                   => C3_MEM_BURST_LEN,
   C_MEM_CAS_LATENCY                 => C3_MEM_CAS_LATENCY,
   C_MEM_ADDR_WIDTH                  => C3_MEM_ADDR_WIDTH,
   C_MEM_BANKADDR_WIDTH              => C3_MEM_BANKADDR_WIDTH,
   C_MEM_NUM_COL_BITS                => C3_MEM_NUM_COL_BITS,
   C_MEM_DDR1_2_ODS                  => C3_MEM_DDR1_2_ODS,
   C_MEM_DDR2_RTT                    => C3_MEM_DDR2_RTT,
   C_MEM_DDR2_DIFF_DQS_EN            => C3_MEM_DDR2_DIFF_DQS_EN,
   C_MEM_DDR2_3_PA_SR                => C3_MEM_DDR2_3_PA_SR,
   C_MEM_DDR2_3_HIGH_TEMP_SR         => C3_MEM_DDR2_3_HIGH_TEMP_SR,
   C_MEM_DDR3_CAS_LATENCY            => C3_MEM_DDR3_CAS_LATENCY,
   C_MEM_DDR3_ODS                    => C3_MEM_DDR3_ODS,
   C_MEM_DDR3_RTT                    => C3_MEM_DDR3_RTT,
   C_MEM_DDR3_CAS_WR_LATENCY         => C3_MEM_DDR3_CAS_WR_LATENCY,
   C_MEM_DDR3_AUTO_SR                => C3_MEM_DDR3_AUTO_SR,
   C_MEM_DDR3_DYN_WRT_ODT            => C3_MEM_DDR3_DYN_WRT_ODT,
   C_MEM_MOBILE_PA_SR                => C3_MEM_MOBILE_PA_SR,
   C_MEM_MDDR_ODS                    => C3_MEM_MDDR_ODS,
   C_MC_CALIB_BYPASS                 => C3_MC_CALIB_BYPASS,
   C_MC_CALIBRATION_MODE             => C3_MC_CALIBRATION_MODE,
   C_MC_CALIBRATION_DELAY            => C3_MC_CALIBRATION_DELAY,
   C_SKIP_IN_TERM_CAL                => C3_SKIP_IN_TERM_CAL,
   C_SKIP_DYNAMIC_CAL                => C3_SKIP_DYNAMIC_CAL,
   C_LDQSP_TAP_DELAY_VAL             => C3_LDQSP_TAP_DELAY_VAL,
   C_LDQSN_TAP_DELAY_VAL             => C3_LDQSN_TAP_DELAY_VAL,
   C_UDQSP_TAP_DELAY_VAL             => C3_UDQSP_TAP_DELAY_VAL,
   C_UDQSN_TAP_DELAY_VAL             => C3_UDQSN_TAP_DELAY_VAL,
   C_DQ0_TAP_DELAY_VAL               => C3_DQ0_TAP_DELAY_VAL,
   C_DQ1_TAP_DELAY_VAL               => C3_DQ1_TAP_DELAY_VAL,
   C_DQ2_TAP_DELAY_VAL               => C3_DQ2_TAP_DELAY_VAL,
   C_DQ3_TAP_DELAY_VAL               => C3_DQ3_TAP_DELAY_VAL,
   C_DQ4_TAP_DELAY_VAL               => C3_DQ4_TAP_DELAY_VAL,
   C_DQ5_TAP_DELAY_VAL               => C3_DQ5_TAP_DELAY_VAL,
   C_DQ6_TAP_DELAY_VAL               => C3_DQ6_TAP_DELAY_VAL,
   C_DQ7_TAP_DELAY_VAL               => C3_DQ7_TAP_DELAY_VAL,
   C_DQ8_TAP_DELAY_VAL               => C3_DQ8_TAP_DELAY_VAL,
   C_DQ9_TAP_DELAY_VAL               => C3_DQ9_TAP_DELAY_VAL,
   C_DQ10_TAP_DELAY_VAL              => C3_DQ10_TAP_DELAY_VAL,
   C_DQ11_TAP_DELAY_VAL              => C3_DQ11_TAP_DELAY_VAL,
   C_DQ12_TAP_DELAY_VAL              => C3_DQ12_TAP_DELAY_VAL,
   C_DQ13_TAP_DELAY_VAL              => C3_DQ13_TAP_DELAY_VAL,
   C_DQ14_TAP_DELAY_VAL              => C3_DQ14_TAP_DELAY_VAL,
   C_DQ15_TAP_DELAY_VAL              => C3_DQ15_TAP_DELAY_VAL
   )
port map
(
   mcb3_dram_dq                        => mcb3_dram_dq,
   mcb3_dram_a                         => mcb3_dram_a,
   mcb3_dram_ba                        => mcb3_dram_ba,
   mcb3_dram_cke                       => mcb3_dram_cke,
   mcb3_dram_ras_n                     => mcb3_dram_ras_n,
   mcb3_dram_cas_n                     => mcb3_dram_cas_n,
   mcb3_dram_we_n                      => mcb3_dram_we_n,
   mcb3_dram_dm                        => mcb3_dram_dm,
   mcb3_dram_udqs                      => mcb3_dram_udqs,
   mcb3_rzq                             => mcb3_rzq,
   mcb3_dram_udm                       => mcb3_dram_udm,
   calib_done                      => c3_calib_done,
   async_rst                       => c3_async_rst,
   sysclk_2x                       => c3_sysclk_2x,
   sysclk_2x_180                   => c3_sysclk_2x_180,
   pll_ce_0                        => c3_pll_ce_0,
   pll_ce_90                       => c3_pll_ce_90,
   pll_lock                        => c3_pll_lock,
   mcb_drp_clk                     => c3_mcb_drp_clk,
   mcb3_dram_dqs                       => mcb3_dram_dqs,
   mcb3_dram_ck                        => mcb3_dram_ck,
   mcb3_dram_ck_n                      => mcb3_dram_ck_n,
   p0_cmd_clk                           =>  c3_clk0,
   p0_cmd_en                            =>  c3_p0_cmd_en,
   p0_cmd_instr                         =>  c3_p0_cmd_instr,
   p0_cmd_bl                            =>  c3_p0_cmd_bl,
   p0_cmd_byte_addr                     =>  c3_p0_cmd_byte_addr,
   p0_cmd_empty                         =>  c3_p0_cmd_empty,
   p0_cmd_full                          =>  c3_p0_cmd_full,
   p0_wr_clk                            =>  c3_clk0,
   p0_wr_en                             =>  c3_p0_wr_en,
   p0_wr_mask                           =>  c3_p0_wr_mask,
   p0_wr_data                           =>  c3_p0_wr_data,
   p0_wr_full                           =>  c3_p0_wr_full,
   p0_wr_empty                          =>  c3_p0_wr_empty,
   p0_wr_count                          =>  c3_p0_wr_count,
   p0_wr_underrun                       =>  c3_p0_wr_underrun,
   p0_wr_error                          =>  c3_p0_wr_error,
   p0_rd_clk                            =>  c3_clk0,
   p0_rd_en                             =>  c3_p0_rd_en,
   p0_rd_data                           =>  c3_p0_rd_data,
   p0_rd_full                           =>  c3_p0_rd_full,
   p0_rd_empty                          =>  c3_p0_rd_empty,
   p0_rd_count                          =>  c3_p0_rd_count,
   p0_rd_overflow                       =>  c3_p0_rd_overflow,
   p0_rd_error                          =>  c3_p0_rd_error,
   selfrefresh_enter                    =>  c3_selfrefresh_enter,
   selfrefresh_mode                     =>  c3_selfrefresh_mode
);

 memc3_tb_top_inst : memc3_tb_top

generic map
 (
   C_SIMULATION                      => C3_SIMULATION,
   C_P0_MASK_SIZE                    => C3_P0_MASK_SIZE,
   C_P0_DATA_PORT_SIZE               => C3_P0_DATA_PORT_SIZE,
   C_NUM_DQ_PINS                     => C3_NUM_DQ_PINS,
   C_MEM_BURST_LEN                   => C3_MEM_BURST_LEN,
   C_MEM_NUM_COL_BITS                => C3_MEM_NUM_COL_BITS,
   C_SMALL_DEVICE                    => C3_SMALL_DEVICE,
   C_p0_BEGIN_ADDRESS                       =>  C3_p0_BEGIN_ADDRESS, 
   C_p0_END_ADDRESS                         =>  C3_p0_END_ADDRESS 
   )
port map
(
   error                           => c3_error,
   calib_done                      => c3_calib_done,
   clk0                            => c3_clk0,
   rst0                            => c3_rst0,
   cmp_error                       => c3_cmp_error,
   cmp_data_valid                  => c3_cmp_data_valid,
   cmp_data                        => c3_cmp_data,
   p0_mcb_cmd_en_o                          =>  c3_p0_cmd_en,
   p0_mcb_cmd_instr_o                       =>  c3_p0_cmd_instr,
   p0_mcb_cmd_bl_o                          =>  c3_p0_cmd_bl,
   p0_mcb_cmd_addr_o                        =>  c3_p0_cmd_byte_addr,
   p0_mcb_cmd_full_i                        =>  c3_p0_cmd_full,
   p0_mcb_wr_en_o                           =>  c3_p0_wr_en,
   p0_mcb_wr_mask_o                         =>  c3_p0_wr_mask,
   p0_mcb_wr_data_o                         =>  c3_p0_wr_data,
   p0_mcb_wr_full_i                         =>  c3_p0_wr_full,
   p0_mcb_wr_fifo_counts                    =>  c3_p0_wr_count,
   p0_mcb_wr_empty_i                        =>  c3_p0_wr_empty,
   p0_mcb_rd_en_o                           =>  c3_p0_rd_en,
   p0_mcb_rd_data_i                         =>  c3_p0_rd_data,
   p0_mcb_rd_empty_i                        =>  c3_p0_rd_empty,
   p0_mcb_rd_fifo_counts                    =>  c3_p0_rd_count,
--   Va => Va
  );

 
   gen_dbg_enable:if (DEBUG_EN = 1) generate 
     -- controller 3
--avt     c3_dbg_data(255 downto 0) <= ( c3_zeroes1 &
--avt			      c3_cmp_error &
     c3_dbg_data(255 downto 0) <= ( c3_zeroes1 &
			      c3_calib_done & 
			      c3_error &
			      c3_cmp_error &  
			      c3_cmp_data &
                              c3_cmp_data_valid &  
			      c3_p0_cmd_en &
			      c3_p0_cmd_instr &
			      c3_p0_cmd_bl &
			      c3_p0_cmd_byte_addr &
			      c3_p0_cmd_empty &
			      c3_p0_cmd_full &

			      c3_p0_rd_en &
			      c3_p0_rd_data(31 downto 0) &
			      c3_p0_rd_full &
			      c3_p0_rd_empty &
			      c3_p0_rd_count &
			      c3_p0_rd_overflow &
			      c3_p0_rd_error &

			      c3_p0_wr_en &
			      c3_p0_wr_mask(3 downto 0) &
			      c3_p0_wr_data(31 downto 0) &
			      c3_p0_wr_full &
			      c3_p0_wr_empty &
			      c3_p0_wr_count &
			      c3_p0_wr_underrun &
			      c3_p0_wr_error
				); 

  c3_dbg_trig(1 downto 0) <=  ( c3_calib_done & c3_error );



  c3_vio_modify_enable   <= c3_vio_out(6); 
  c3_vio_addr_mode_value <= c3_vio_out(2 downto 0);   

  bigger_device: if (C3_SMALL_DEVICE = "FALSE") generate
     -- Drive data mode through VIO core for bigger devices
     c3_vio_data_mode_value <= c3_vio_out(5 downto 3);  
  end generate;

  small_device: if (not(C3_SMALL_DEVICE = "FALSE")) generate
     -- Drive a constant data mode value for smaller devices
     c3_vio_data_mode_value <= "010";  
  end generate;

    -----------------------------------------------------------------------------
   --  ICON core instance
   -----------------------------------------------------------------------------
    my_icon_c3 : icon port map
     (
      CONTROL0 =>  c3_control0,
      CONTROL1 =>  c3_control1 
      );
   -----------------------------------------------------------------------------
   --  ILA core instance
   -----------------------------------------------------------------------------
    my_ila_c3 : ila port map
     (
      CONTROL => c3_control0,
      CLK     => c3_clk0,
      DATA    => c3_dbg_data,
      TRIG0   => c3_dbg_trig 
      );
	
   -----------------------------------------------------------------------------
   --  VIO core instance
   -----------------------------------------------------------------------------
   my_vio_c3 : vio port map
   (
      CONTROL    => c3_control1,
      ASYNC_OUT  => c3_vio_out
      );  

   end generate;
	
  

 end  arc;

this is the top example

 

[TrickyDicky]

Ok - that doesnt really help. I dont really see what you're trying to do. But I think you want to make Va and input to the system, not an inout.
But you never said what the error was when you did this.

 

[hannachifaten]

Ok - that doesnt really help. I dont really see what you're trying to do. But I think you want to make Va and input to the system, not an inout.
But you never said what the error was when you did this.

ok that ok , i think that i fixed the problem , but when the simlutaion screen appears i dont see TEST PASSED even though the results are corrects ,
So what happened during simulation , is it correct ??


few hours , i want to modify the writing data , i want to write some data which change of value every cycle for example ( i put my desired data in the top of module after that this data will be changed or generated by another block that it was the aim of this program) i test this in test bench file
just an idea to read and write to my DDR

i thank you a lot

 

[hannachifaten]

hello , i come back to ask people some few question : for who know working by DDR and Mig Tools : i need some response please , i know that i'm asking very much but i want to take advanteges from this training ,

first of all , i generate mcb BLOCK by using the MIG , and i choose working without Traffic generator which is located in example design/PAR in output files of MIG
after that i write my code which is a state machine in the test bench of my user interface ( mem3_tb.vhd)
- i add data there it simulated well , but my question : this data will be generated only in this file ? can i modify this data without writing in the test bench ?
- how can i generate a variable date and will be come to this file
- I ask you if i can make an input in the top design such as constant not in the test bench
- Finally i don't know how to connect my input data without giving a value in the test bench if i intialise this in the to design ( i give a value in the top design for example ) ???? i don't know how asking you :-| i hope that some one understand me :-/

 

[syedshan]

hi

I think you need to goto xilinx forum. register there and read the queries similar to you have to understanding. This is how i started. I cannot help on spartan-6 design since I did not work. Basics I told you earlier. That you have to make your own traffic generator.

If you read, re-read the posts on the forums, then you might understand the things more. initially it takes time. That is normal.

For now, I think you are doing it nor very much right a/c to above final post.