vivek_p
Advanced Member level 4
Synthesis
reg a;
wire b;
always@(posedge clk)
begin
if(rst)
a< =1'b0;
else
a <=b;
end
Here "a" is a D-Flip Flop. If I synthesis the design using Synopsys Design Compiler how many transistors will be inferred for "a"..............
reg a;
wire b;
always@(posedge clk)
begin
if(rst)
a< =1'b0;
else
a <=b;
end
Here "a" is a D-Flip Flop. If I synthesis the design using Synopsys Design Compiler how many transistors will be inferred for "a"..............