how many times need to test a 8-bit bus to make sure it work?

[onion2014]

hi all, that's the question, thanks.

 

[barry]

6.5 billion times is the industry standard. Set all bits to logic 1, wait for 1 second, then set all bits to logic 0. Do this 6.5 billion times.

 

[onion2014]

6.5 billion times is the industry standard. Set all bits to logic 1, wait for 1 second, then set all bits to logic 0. Do this 6.5 billion times.

so this will consume 6.5billion*1s? Why set all to 1 and then set all to 0? I am still confused about it. Would you please give more detail. I am a beginner. Does test time changes with the bus width? Thanks in advance.

 

[barry]

I was joking; 6.5 billion seconds and we will both be long dead.

Your question doesn't really make sense; it's not really a question of "how many times" to test it. If your test is properly designed you only need to test it once. You need to think about exactly WHAT it is you are testing: timing? voltage levels? current drive?

 

[onion2014]

:lol: I agree with you. Might if we want to test the voltage, we can just set all to 1 except only one to 0, and do this 8 times. It's right? I mean just to test whether there is short circuit in the bus. What should we do to test the timing and current drive?

I was joking; 6.5 billion seconds and we will both be long dead.

Your question doesn't really make sense; it's not really a question of "how many times" to test it. If your test is properly designed you only need to test it once. You need to think about exactly WHAT it is you are testing: timing? voltage levels? current drive?

 

[barry]

Yes, you're on the right track.

To test timing, you need to know what it's SUPPOSED to be. Do you have some READ or WRITE signal associated with the bus? How about a clock? You need to verify that the data setup and hold times are met, within some margin.

What is your expected load? Put that load on the bus and verify that the voltages are still within spec. (This is probably not a real high-priority test, unless the bus is going off the board).

Is this bus going off-board, or just from one chip to another? HOW your bus is used will determine what really needs to be tested.

 

[onion2014]

Yes, for timing constraint, I should verify the setup/hold time relative to clk or control signals. and also need to add the load to see whether the voltage still can reach the desire voltage in a certain period. Thanks a lot.:-D

Yes, you're on the right track.

To test timing, you need to know what it's SUPPOSED to be. Do you have some READ or WRITE signal associated with the bus? How about a clock? You need to verify that the data setup and hold times are met, within some margin.

What is your expected load? Put that load on the bus and verify that the voltages are still within spec. (This is probably not a real high-priority test, unless the bus is going off the board).

Is this bus going off-board, or just from one chip to another? HOW your bus is used will determine what really needs to be tested.