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Hi all, I write a vhdl code on ISE xilinx and I want to know how much time my application may take to be executed, I was told that we can get this estimation from the Implement report but I don't Know where.
You have a synthesis report, a translate report, a map report, a PAR report and they ALL tell you how long they took to complete. I'm not sure what you mean by "Implementation Report". What version of ISE are you using?
Hi barry, after I implement the design a "Timing constraint" report and "clock report" appear, I would know how long my application may take once data enters the FPGA to get output. There is many informations in the "Timing constraint" and "clock report" reports and I get confused.
Oh, you want to know your TIMING, not how long it takes to compile, right?
The timing report only tells you the how fast the device can run; it has NOTHING to do with the input-to-output relationship-that's totally dependent on your application. Does your input get shifted through 10 registers? 100? A million? The best solution is to run a simulation.
Hi again, thanks barry for your response, it is just my problem I get my Timing after many tests on simulation, in my case it take 1.6 us. if i run a simulation for a period under 1.6 us I get a false results or if I do this :
P1 <= "0110" after 0 ns, "1111" after 1,5 us I will have false results too.
So what I must do is : P1 <= "0110" after 0 ns, "1111" after 1.6 us, In this case I will get a good results.
Is there any way to have an estimation of my Timing before i begin the simulation?