I had a question, For or loop in Verilog how is executed? Sequential or parallel?
My qustion assignment in for executed in parallel mode?
can any one guide me??
Code:
module for_loop_simulation ();
integer ii=0;
reg [7:0] r_Data[5:0]; // Create reg 8 bit wide by 6 words deep.
initial
begin
for (ii=0; ii<6; ii=ii+1)
begin
r_Data[ii] = ii*ii;
$display("Time %2d: r_Data at Index %1d is %2d", $time, ii, r_Data[ii]);
end
end
endmodule
I had a question, For or loop in Verilog how is executed? Sequential or parallel?
My qustion assignment in for executed in parallel mode?
can any one guide me??
Code:
module for_loop_simulation ();
integer ii=0;
reg [7:0] r_Data[5:0]; // Create reg 8 bit wide by 6 words deep.
initial
begin
for (ii=0; ii<6; ii=ii+1)
begin
r_Data[ii] = ii*ii;
$display("Time %2d: r_Data at Index %1d is %2d", $time, ii, r_Data[ii]);
end
end
endmodule
No difference. In the context of an initial block, both codes aren't actually synthesizing logic, only initializing variables that are acting as constants.
No difference. In the context of an initial block, both codes aren't actually synthesizing logic, only initializing variables that are acting as constants.
As long as r_Data isn't assigned other values in other parts of the always block, it's still acting as constant. And if r_Data is never read anywhere, it will be discarded in synthesis.
Questions about HDL synthesis based on incomplete code snippets have rarely clear answers. You should at least provide a complete module with in- and outputs.