Nov 11, 2015 #1 M milan.km Member level 3 Joined Sep 14, 2015 Messages 55 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 435 hi. does BRAM read accesses are characterized by a latency of two clock cycles (one to latch the address, and a subsequent one to latch data on the output) ?
hi. does BRAM read accesses are characterized by a latency of two clock cycles (one to latch the address, and a subsequent one to latch data on the output) ?
Nov 11, 2015 #2 D.A.(Tony)Stewart Advanced Member level 7 Joined Sep 26, 2007 Messages 9,071 Helped 1,825 Reputation 3,649 Reaction score 2,222 Trophy points 1,413 Location Richmond Hill, ON, Canada Activity points 59,846 https://www.opalkelly.com/examples/accessing-bram-xilinx/
Nov 11, 2015 #3 M milan.km Member level 3 Joined Sep 14, 2015 Messages 55 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 435 i didnt get my answer.
Nov 11, 2015 #4 V vGoodtimes Advanced Member level 4 Joined Feb 16, 2015 Messages 1,089 Helped 307 Reputation 614 Reaction score 303 Trophy points 83 Activity points 8,730 it is configurable, either 1 or 2. https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf 2 cycles mode has a lower clock to out.
it is configurable, either 1 or 2. https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf 2 cycles mode has a lower clock to out.