How instructions like JM JNZ and JZ work ?

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Lord Loh.

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CPU architecture....

Can any one tell me how instructions like JM JNZ and JZ work ?

I understand the CPUs use a contol ROM with micro instructions saved in it to perform operations. The contitional Jumps take 17 clock cycles to execute. And how is the output of a control ROM modified depending on the ZERO and SIGN flag?

I would understand the control Matrix doing so but I am just unable to comprehend how the Control ROM does so....

Please guide me....

Thank you.
 

Re: CPU architecture....

Processors have registers (addresable internal memory blocks), flags regiter, consist array of flags zero and sign flags from this array. Some arifmetical, logical, special operations modifies this flags (in most purposes depend operation DST status).
Obtain documentation of your processor from manufacturer.
 

CPU architecture....

I understood it a few days later by reading "Structured computer organization" by Tenenbaum.

The key is that the instructions that correspond to the jump case and not to jump case is not in the memory sequentially...

The instructions in the control ROM is not sequencial...

The higher order adresses are set by the zero and minus flag where needed...

Hope I explained it here well.....(I understand it fine in my brain...)

This thread is quite old...I lost all hopes of having a reply ...
 

CPU architecture....

I beg your pardon... What is ESD ? I am not able to follow you at all...

All I wanted to know was how JZ and JMP and JNZ type of commands worked. And the clue wa that the microinstruction for these are not stored in a sequential manner in the control ROM...
 

CPU architecture....

How works Jcc (JZ, JNZ, etc) instruction?
This is full his pescription: And this is examle of instruction that change flags:
 

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