How instructions like JM JNZ and JZ work ?

[Lord Loh.]

CPU architecture....

Can any one tell me how instructions like JM JNZ and JZ work ?

I understand the CPUs use a contol ROM with micro instructions saved in it to perform operations. The contitional Jumps take 17 clock cycles to execute. And how is the output of a control ROM modified depending on the ZERO and SIGN flag?

I would understand the control Matrix doing so but I am just unable to comprehend how the Control ROM does so....

Please guide me....

Thank you.

 

[Frank32]

Re: CPU architecture....

Processors have registers (addresable internal memory blocks), flags regiter, consist array of flags zero and sign flags from this array. Some arifmetical, logical, special operations modifies this flags (in most purposes depend operation DST status).
Obtain documentation of your processor from manufacturer.

 

[nand_gates]

Re: CPU architecture....

Check the link below!


https://www10.dacafe.com/book/parse_book.php?article=BITSLICE/BIT_CHAP_2/bislcC2B2.html

Hope this helps

 

[Lord Loh.]

CPU architecture....

I understood it a few days later by reading "Structured computer organization" by Tenenbaum.

The key is that the instructions that correspond to the jump case and not to jump case is not in the memory sequentially...

The instructions in the control ROM is not sequencial...

The higher order adresses are set by the zero and minus flag where needed...

Hope I explained it here well.....(I understand it fine in my brain...)

This thread is quite old...I lost all hopes of having a reply ...

 

[Lord Loh.]

CPU architecture....

I beg your pardon... What is ESD ? I am not able to follow you at all...

All I wanted to know was how JZ and JMP and JNZ type of commands worked. And the clue wa that the microinstruction for these are not stored in a sequential manner in the control ROM...

 

[Frank32]

CPU architecture....

How works Jcc (JZ, JNZ, etc) instruction?
This is full his pescription:

**broken link removed**, Intel

Jcc -- Jump if Condition is Met

Opcode Instruction Clocks Description

77 cb JA rel8 7+m,3 Jump short if above (CF=0 and ZF=0)
73 cb JAE rel8 7+m,3 Jump short if above or equal (CF=0)
72 cb JB rel8 7+m,3 Jump short if below (CF=1)
76 cb JBE rel8 7+m,3 Jump short if below or equal (CF=1 or ZF=1)
72 cb JC rel8 7+m,3 Jump short if carry (CF=1)
E3 cb JCXZ rel8 9+m,5 Jump short if CX register is 0
E3 cb JECXZ rel8 9+m,5 Jump short if ECX register is 0
74 cb JE rel8 7+m,3 Jump short if equal (ZF=1)
74 cb JZ rel8 7+m,3 Jump short if 0 (ZF=1)
7F cb JG rel8 7+m,3 Jump short if greater (ZF=0 and SF=OF)
7D cb JGE rel8 7+m,3 Jump short if greater or equal (SF=OF)
7C cb JL rel8 7+m,3 Jump short if less (SF<>OF)
7E cb JLE rel8 7+m,3 Jump short if less or equal (ZF=1 and SF<>OF)
76 cb JNA rel8 7+m,3 Jump short if not above (CF=1 or ZF=1)
72 cb JNAE rel8 7+m,3 Jump short if not above or equal (CF=1)
73 cb JNB rel8 7+m,3 Jump short if not below (CF=0)
77 cb JNBE rel8 7+m,3 Jump short if not below or equal (CF=0 and ZF=0)
73 cb JNC rel8 7+m,3 Jump short if not carry (CF=0)
75 cb JNE rel8 7+m,3 Jump short if not equal (ZF=0)
7E cb JNG rel8 7+m,3 Jump short if not greater (ZF=1 or SF<>OF)
7C cb JNGE rel8 7+m,3 Jump short if not greater or equal (SF<>OF)
7D cb JNL rel8 7+m,3 Jump short if not less (SF=OF)
7F cb JNLE rel8 7+m,3 Jump short if not less or equal (ZF=0 and SF=OF)
71 cb JNO rel8 7+m,3 Jump short if not overflow (OF=0)
7B cb JNP rel8 7+m,3 Jump short if not parity (PF=0)
79 cb JNS rel8 7+m,3 Jump short if not sign (SF=0)
75 cb JNZ rel8 7+m,3 Jump short if not zero (ZF=0)
70 cb JO rel8 7+m,3 Jump short if overflow (OF=1)
7A cb JP rel8 7+m,3 Jump short if parity (PF=1)
7A cb JPE rel8 7+m,3 Jump short if parity even (PF=1)
7B cb JPO rel8 7+m,3 Jump short if parity odd (PF=0)
78 cb JS rel8 7+m,3 Jump short if sign (SF=1)
74 cb JZ rel8 7+m,3 Jump short if zero (ZF = 1)
0F 87 cw/cd JA rel16/32 7+m,3 Jump near if above (CF=0 and ZF=0)
0F 83 cw/cd JAE rel16/32 7+m,3 Jump near if above or equal (CF=0)
0F 82 cw/cd JB rel16/32 7+m,3 Jump near if below (CF=1)
0F 86 cw/cd JBE rel16/32 7+m,3 Jump near if below or equal (CF=1 or ZF=1)
0F 82 cw/cd JC rel16/32 7+m,3 Jump near if carry (CF=1)
0F 84 cw/cd JE rel16/32 7+m,3 Jump near if equal (ZF=1)
0F 84 cw/cd JZ rel16/32 7+m,3 Jump near if 0 (ZF=1)
0F 8F cw/cd JG rel16/32 7+m,3 Jump near if greater (ZF=0 and SF=OF)
0F 8D cw/cd JGE rel16/32 7+m,3 Jump near if greater or equal (SF=OF)
0F 8C cw/cd JL rel16/32 7+m,3 Jump near if less (SF<>OF)
0F 8E cw/cd JLE rel16/32 7+m,3 Jump near if less or equal (ZF=1 and SF<>OF)
0F 86 cw/cd JNA rel16/32 7+m,3 Jump near if not above (CF=1 or ZF=1)
0F 82 cw/cd JNAE rel16/32 7+m,3 Jump near if not above or equal (CF=1)
0F 83 cw/cd JNB rel16/32 7+m,3 Jump near if not below (CF=0)
0F 87 cw/cd JNBE rel16/32 7+m,3 Jump near if not below or equal (CF=0 and ZF=0)
0F 83 cw/cd JNC rel16/32 7+m,3 Jump near if not carry (CF=0)
0F 85 cw/cd JNE rel16/32 7+m,3 Jump near if not equal (ZF=0)
0F 8E cw/cd JNG rel16/32 7+m,3 Jump near if not greater (ZF=1 or SF<>OF)
0F 8C cw/cd JNGE rel16/32 7+m,3 Jump near if not greater or equal (SF<>OF)
0F 8D cw/cd JNL rel16/32 7+m,3 Jump near if not less (SF=OF)
0F 8F cw/cd JNLE rel16/32 7+m,3 Jump near if not less or equal (ZF=0 and SF=OF)
0F 81 cw/cd JNO rel16/32 7+m,3 Jump near if not overflow (OF=0)
0F 8B cw/cd JNP rel16/32 7+m,3 Jump near if not parity (PF=0)
0F 89 cw/cd JNS rel16/32 7+m,3 Jump near if not sign (SF=0)
0F 85 cw/cd JNZ rel16/32 7+m,3 Jump near if not zero (ZF=0)
0F 80 cw/cd JO rel16/32 7+m,3 Jump near if overflow (OF=1)
0F 8A cw/cd JP rel16/32 7+m,3 Jump near if parity (PF=1)
0F 8A cw/cd JPE rel16/32 7+m,3 Jump near if parity even (PF=1)
0F 8B cw/cd JPO rel16/32 7+m,3 Jump near if parity odd (PF=0)
0F 88 cw/cd JS rel16/32 7+m,3 Jump near if sign (SF=1)
0F 84 cw/cd JZ rel16/32 7+m,3 Jump near if 0 (ZF=1)


---------------------------------------------------------------------------
NOTES:
The first clock count is for the true condition (branch taken); the
second clock count is for the false condition (branch not taken). rel16/32
indicates that these instructions map to two; one with a 16-bit relative
displacement, the other with a 32-bit relative displacement, depending on
the operand-size attribute of the instruction.
---------------------------------------------------------------------------

Operation

IF condition
THEN
EIP <- EIP + SignExtend(rel8/16/32);
IF OperandSize = 16
THEN EIP <- EIP AND 0000FFFFH;
FI;
FI;

Description

Conditional jumps (except JCXZ) test the flags which have been set by
a previous instruction. The conditions for each mnemonic are given in
parentheses after each description above. The terms "less" and "greater"
are used for comparisons of signed integers; "above" and "below" are
used for unsigned integers.

If the given condition is true, a jump is made to the location provided as
the operand. Instruction coding is most efficient when the target for the
conditional jump is in the current code segment and within -128 to
+127 bytes of the next instruction's first byte. The jump can also target
-32768 thru +32767 (segment size attribute 16) or -2^(31) thru +2^(31) -1
(segment size attribute 32) relative to the next instruction's first byte.
When the target for the conditional jump is in a different segment, use
the opposite case of the jump instruction (i.e., JE and JNE), and then
access the target with an unconditional far jump to the other segment.
For example, you cannot code--

JZ FARLABEL;

You must instead code--

JNZ BEYOND;
JMP FARLABEL;
BEYOND:

Because there can be several ways to interpret a particular state of the
flags, ASM386 provides more than one mnemonic for most of the
conditional jump opcodes. For example, if you compared two characters in
AX and want to jump if they are equal, use JE; or, if you ANDed AX
with a bit field mask and only want to jump if the result is 0, use JZ, a
synonym for JE.

JCXZ differs from other conditional jumps because it tests the contents of
the CX or ECX register for 0, not the flags. JCXZ is useful at the beginning
of a conditional loop that terminates with a conditional loop instruction
(such as LOOPNE TARGET LABEL. The JCXZ prevents entering the loop with CX or
ECX equal to zero, which would cause the loop to execute 64K or 32G times
instead of zero times.

Flags Affected

None

Protected Mode Exceptions

#GP(0) if the offset jumped to is beyond the limits of the code segment

Real Address Mode Exceptions

None

Virtual 8086 Mode Exceptions

None

And this is examle of instruction that change flags:

**broken link removed**, Intel


CMP -- Compare Two Operands

Opcode Instruction Clocks Description

3C ib CMP AL,imm8 2 Compare immediate byte to AL
3D iw CMP AX,imm16 2 Compare immediate word to AX
3D id CMP EAX,imm32 2 Compare immediate dword to EAX
80 /7 ib CMP r/m8,imm8 2/5 Compare immediate byte to r/m byte
81 /7 iw CMP r/m16,imm16 2/5 Compare immediate word to r/m word
81 /7 id CMP r/m32,imm32 2/5 Compare immediate dword to r/m dword
83 /7 ib CMP r/m16,imm8 2/5 Compare sign extended immediate byte to r/m word
83 /7 ib CMP r/m32,imm8 2/5 Compare sign extended immediate byte to r/m dword
38 /r CMP r/m8,r8 2/5 Compare byte register to r/m byte
39 /r CMP r/m16,r16 2/5 Compare word register to r/m word
39 /r CMP r/m32,r32 2/5 Compare dword register to r/m dword
3A /r CMP r8,r/m8 2/6 Compare r/m byte to byte register
3B /r CMP r16,r/m16 2/6 Compare r/m word to word register
3B /r CMP r32,r/m32 2/6 Compare r/m dword to dword register

Operation

LeftSRC - SignExtend(RightSRC);
(* CMP does not store a result; its purpose is to set the flags *)

Description

CMP subtracts the second operand from the first but, unlike the SUB
instruction, does not store the result; only the flags are changed. CMP is
typically used in conjunction with conditional jumps and the SETcc
instruction. (Refer to Appendix D for the list of signed and unsigned flag
tests provided.) If an operand greater than one byte is compared to an
immediate byte, the byte value is first sign-extended.

Flags Affected

OF, SF, ZF, AF, PF, and CF as described in Appendix C

Protected Mode Exceptions

#GP(0) for an illegal memory operand effective address in the CS, DS, ES,
FS, or GS segments; #SS(0) for an illegal address in the SS segment;
#PF(fault-code) for a page fault

Real Address Mode Exceptions

Interrupt 13 if any part of the operand would lie outside of the effective
address space from 0 to 0FFFFH

Virtual 8086 Mode Exceptions

Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault