How if and case statements infer logic after synthesis?

dsairajkiran · May 14, 2007

can anyone explain how if and case statements infer logic after synthesis ?

arp · May 14, 2007

if vs case verilog

If statement used for priority encoder
where as
case statement is used for Mux

deepu_s_s · May 14, 2007

Re: if vs case verilog

these are conditional statements and any synthesizer infer them as a mux.

naveenkrishnan · May 14, 2007

Re: if vs case verilog

It all depends on how you code. Even with if, you can create parallel mux implementation. Similarly, you can get a priority encoder with case and proper synopsys synthesis directives.

Read the following papers:
http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf
**broken link removed**

Naveen
www.vlsiforum.com

Privacy & Transparency