how gate length or technology in cmos is decided

[Yathin P U]

How is the technology ie gate length such as 180nm, 90nm, 65nm, 45nm, 20nm, etc decided ? How is it chosen ? Why other gate lengths are not used as cmos technology ?
What are the criteria to choose such specific numbers ?

 

[dick_freebird]

The nominal gate length is also a proxy for many other
process attributes. Some are co-scaled and some are
just "shiny new equipment for all".

For example there is no value in having a thicker gate
ox than your minimum L can reliably stand off the same
voltage, for. You can go higher in L, if you want, but
the technology is always developed against speed and
power and density goals because analog guys don't
fill fabs.

Things like interconnect pitch tend to follow the tool
set that defines the gate, but at a safe distance. So
you may see 0.8um metal pitch on 0.18um and 0.5um
pitch on 90nm (just an example, not from anyone's PDK).

Newer nodes cost -way- more up front and per wafer,
and only somebody with a big demand or access to some
multiproject service can make sense of the pricing these
days. If your project does not need 20nm (and you, on
your own, almost certainly cannot string together enough
transistors in a year's time to fill the reticle, so you don't -
your 20-man team with a fat reuse library behind it and
synthesis as the design method, might) then there is no
good reason to go there. Buy what you need and no more.
That's engineering economics 101.

 

[Yathin P U]

I am afraid, i did not understand from your post. Can you please explain it in a different way ?

 

[leo_o2]

From technolog view, any other length can be chosen for next generation node.
However, it is economy drive to achieve significant cost-down.
For digital circuit, it might be 1/2 shrink if length is reduced by 1/sqrt(2).
However, some foundry jump more than it.

 

[Junus2012]

the analog design guys do not follow the minimum channel length technology, for example: if the channel length is 180 nm, the designers use 0.35 µm in order to avoid the channel length modulation and small channel length effects.

How is the technology ie gate length such as 180nm, 90nm, 65nm, 45nm, 20nm, etc decided ? How is it chosen ? Why other gate lengths are not used as cmos technology ?
What are the criteria to choose such specific numbers ?

 

[jgk2004]

This is not true. If you are pushing the edge of your technology and getting close to the fT, then you do use minimum length at the cost of gain. This is why in smaller technologies, designs start cascading not cascoding.. you only use 2XLmin and larger for slower stuff.

JGK

the analog design guys do not follow the minimum channel length technology, for example: if the channel length is 180 nm, the designers use 0.35 µm in order to avoid the channel length modulation and small channel length effects.

 

[Yathin P U]

could you please elaborate on this?

 

[Teddy]

smaller gate length is decided long time ago by Mr. Moore and everybody tries to follow.
Every single new technology with smaller geometries IS digital at first. Then the analog support is added. As Dick said - analog rarely fills up the fab. So it is driven by digital and density.