[SOLVED] How famous and important is system C compared to VHDL ?

[MICs]

VHDL vs. SYSTEM C

hello guys,
plz tell me how famous and important is system C compared to VHDL ?

 

[the_penetrator]

Re: VHDL vs. SYSTEM C

They are different languages for (usually) different purposes.

SystemC is for system-level design (transaction-level modeling, evaluating bus architectures with no large pain). VHDL better works from the RTL and below. SystemC won't compile efficiently to RTL VHDL these days either.

I think that many groups use both.

the_penetrator©

 

[cawan]

VHDL vs. SYSTEM C

SystemC, SystemVerilog are defined as System Description Language (SDL)

VHDL, Verilog are defined as Hardware Description Language

SDC need to go through HDL to synthesize the hardware.

 

[wadaye]

Re: VHDL vs. SYSTEM C

Hi MICs:

Both SystemC and VHDL is famous, but they have different useage.

SystemC is used to systemlevel design, and VHDL are used to be

synthesised into gates.

wang1

 

[ram]

VHDL vs. SYSTEM C

There are follwong things where the systemc is superier than VHDl -
1. Verification of Ips
2. Creating models for verification.

VS vhdl is superior for -
RTL coding.

It is very time comsumming to write the testbanch in VHDL. If we use systemc it can give a random data genration with random transactions so u can use ti for testing the systm

 

[haoboy]

VHDL vs. SYSTEM C

system c can also be used in RTL level,but more for system design.

 

[viviwei]

VHDL vs. SYSTEM C

Oh, we can use a old chinese aphorism:Who want to do things better must utilize useful tools.
So, let's use both the tools to do one thing, making things better.

 

[Kermit76]

Re: VHDL vs. SYSTEM C

What is meant by system design? Can't you use either one to accomplish the samething? What are the advantages and disadvantages?

 

[bravobravo]

Re: VHDL vs. SYSTEM C

**broken link removed**

for your to ref only ..