Is there any effect of poly sheet resistance on threshold voltage (Vt), drain current, gm or timing related (i.e. Cgd,Cgs) parameters on PMOS/NMOS devices?
There will be some correlation between the poly doping at
the gate ox interface, and device VT. You can see poly-depletion
effects sometimes if doping is too low or not driven long enough.
Drain risetime will respond to gate resistance and Miller (Cgd)
capacitance. Something like Vgs/Rg=Cdg*dVds/dt. Digital
delay embodies half the output risetime as well as the time
for gate voltage to swing over logic threshold from rest.
Patterned poly resistance (not sheet) will go up as gate length
goes down. To the extent that Leff follows poly litho, you may
see the Rg effect and the Leff cancel somewhat (poorer gate
resistance but stronger drain current).