Code will often have bugs that need to be found and fixed. While there are obvious ways in how to verify VHDL and C/C++ programmes, what method exists to verify and debug timing constrainints e.g expressed in SDC format in Altera TimeQuest?
I prefer the following:
1.) Include the timing score in the FPGA programming file. My designs use 1 BRAM (4kB) to store either a 4kB text file, or a 4kB compressed text file. I then include whatever build/design info I want within this BRAM.
2.) Perform some sanity checks in the sdc/xdc file where possible. For example, ensure some constraints constrain a non-zero number of paths. Basically, if a clock is renamed/removed you should be able to detect it. This means writing something in TCL. (sarcastic) Yay!
3.) Check logs to ensure constraints are not ignored. Ideally this gets moved to #2 over time.
4.) Ensure clock names and other constraints are human-readable and assumptions are well commented.
5.) Where possible, avoid set_false_path. In tools supporting set_data_check, you almost always want that. I'm not sure if Altera has this. I attempted to check, but the documentation site hangs when I try to access it.
6.) Avoid set_multicycle_path unless a testbench can verify this AND the design makes it clear where multicycle paths exist. Either by having clock enabled that are periodically generated, or by having the entire multi-cycle path within a module.
7.) For any high-speed IO interface, provide a mechanism to report on IO status at runtime. Many interfaces can be placed into a test mode for this purpose. Inputs can usually use IO features to measure these things.
8.) Understand the IO requirements of any device you connect to and follow interface requirements. For example, you can have interfaces with a negative setup time. You can have interfaces where hold time is longer than a half-cycle.