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How does FIFO generated with Xilinx coregen work?

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mta97e

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descriptor_fifo : fifo_generator_v2_3
port map (
clk => pci_clk,
din => desc_fifo_wr_data(0),
rd_en => desc_fifo_rd_en(0),
rst => comb_reset(0),
wr_en => desc_fifo_wr_en(0),
data_count => fifo_data_count(0),
dout => desc_fifo_rd_data(0),
empty => desc_fifo_empty(0),
full => open
);

I generate the FIFO of depth 512 and empty treshold of 256. At the initizlization, alll the 512 entries will be filled. The data will be consumed from the FIFO till teh empty treshold point of 256. At that point the interrupt will be generated and software will fill the 256 data entries.

My question is.. I am not sure how the FIFO works.
My understanding is,
1. at initialization all 512 entries are filled. And start to consume from 0 to 255. Interrupt will be generated.
2. 0 to 255 will be filled by software.
3. and what will happen when the reading from FIFO reach 512 ??


What I want to do is everytime there is an empty interrupt, I want to go and fill 256 entries to FIFO. But I dont know which address and when. At address 0 and address 256 alternatively?

I am confused. Someone please enlighten me.
 

gck

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Re: FIFO xilinx coregen

hi,

u need not to worry about address. U just make two pointer one for reading and another for writing.

for empty differance between read and write should be zero and for full differance should be 512.

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

just go through this pdf. though it is for asynchronous but best for reding.
 

    mta97e

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