How does DC insert clock gating cell while doing synthesis?

[vikas_lakhanpal27]

DC clock gating

can some one tell me how DC autmatically inserts clock gating cell while doing Synthesis?

 

[VitalyM4]

Re: DC clock gating

use commands

set_clock_gating_style
and insert_clock_gating

Rgds.

 

[vikas_lakhanpal27]

DC clock gating

Can u expaling how DC does it?Then the RTL to netlist functnality would vary.Right?

 

[VitalyM4]

Re: DC clock gating

Can u expaling how DC does it?Then the RTL to netlist functnality would vary.Right?

It mixes CLOCK_EN and CLK and uses this signal to clock trigger.
Actually there are several types of clock gating (see set_clock_gating_style) Functionality remains the same except you'll have gated clock element. And tools such as Formality can show that both nelist with and without (RTL or netlist) gated clock element have similar functionality if you apply some constraints for tool.