How does a PLL lock ?

[elecomm]

Hi all,
I wanted to ask about PLL, its operation. I read about it some articles and papers but I still cant understand how it locks..also what is the fuction of ( / N) block in the feedback...you can explain to me or send links or books that contain good explanation..
thnx

 

[kazemi]

PLL fundamentals

The block is a frequency divider for example N=10 means frequncy of feedback signal is a tenth of frequncy of output signal.
Also you can use Carlson's book by name"Communication Systems".

 

[rkodaira]

Re: PLL fundamentals

Hi !

A Phase Locked Loop circuit is used to synthesize frequencies from the following blocks: a reference generator, a phase comparator, a low pass filter, a voltage controlled oscillator and the feedback loop (with or without ferquency divider).

In a very simple explanation, PLL works by changing the voltage applied to the VCO, which will generate a signal with frequency proportional to this voltage. This signal originated from the VCO is feedbacked to the phase detector, which compares the phase (and the frequency) of both: the signal generated by the VCO and the signal coming from the Reference Generator. If both signal are in phase and/or same frequency, the phase detector will output a square wave signal, which is passed by the low pass filter, that converts it to an average voltage signal (the mid control voltage) applied to the VCO. When it happens, we say the PLL is locked at the reference frequency. If the VCO outputs a signal with lower frequency than the reference, so the phase detector and the low pass filter will output an higher DC control voltage, so increasing the VCO output frequency, changing it gradually up to the reference frequency. The reverse is true, if the VCO outputs a higher frequency than the reference signal, the phase detector and low pass filter will output a lower dc control voltage, so decreasing the VCO output frequency, until it locks again to the desired frequency.

So imagine that you have a 20MHz crystal oscillator as reference generator, but you need a 80MHz signal at the VCO output. You can use the PLL to multiply and synthesize this higher frequency. Then you divide the VCO output by 4 (the /N block), the signal to be compared with the reference signal has to be 20MHz to lock the PLL, but the VCO is going to generate in fact a 4x frequency signal. The /N block defines the multiplier of reference signal, to be used at the VCO output.

 

[elecomm]

Re: PLL fundamentals

thanx alot, I think i got it.
but again concerning the ( /N )block, I can divide the signal frequency by 2, 4,8 ....using flip-flops only when it is square wave...will this limit the SPECS of any PLL or there is another solution??qnd will the o/p of the VCO be only a square wve or can it be sine wave??

 

[h_ghanei]

PLL fundamentals

PLL uses a VCO (voltage controlled oscilator), LPF (low pass filter) and a PD (phase detector) and its output follows the input (its frquency is equal to f or f/n, that f is the frequency of the input signal)
Its major advantage is to decrease the amplitude noise of the signal.

 

[jawadasheikh]

Re: PLL fundamentals

the signal generated by the VCO and the signal coming from the Reference Generator. If both signal are in phase and/or same frequency, the phase detector will output a square wave signal, which is passed by the low pass filter, that converts it to an average voltage signal (the mid control voltage) applied to the VCO. When it happens, we say the PLL is locked at the reference frequency. If the VCO outputs a signal with lower frequency than the reference, so the phase detector and the low pass filter will output an

 

[andrishev]

Re: PLL fundamentals

it has a charge pump in the output.
When phase error occurs in signals that come from XO and VCO a voltage is charged to VCO to compensate the error.

 

[diemilio]

Re: PLL fundamentals

but again concerning the ( /N )block, I can divide the signal frequency by 2, 4,8 ....using flip-flops only when it is square wave...will this limit the SPECS of any PLL or there is another solution??qnd will the o/p of the VCO be only a square wve or can it be sine wave??

the output signal can be also a sine wave, it depends on the type of PLL you use. check this books out:

Phaselock Techniques by Floyd M. Gardner

Phase-Locked Loops : Design, Simulation, and Applications (Professional Engineering) by Roland E. Best

 

[leoren_tm]

Re: PLL fundamentals

i got this at my email..
Phase_locked_Loops_for_Wireless_Communications___Digital__Analog_and_Optical_Implementations
if you want ill forward it to you...

Added after 9 minutes:

use matlab..hir is a pic of pll in matlab

 

[leoren_tm]

Re: PLL fundamentals

a simulink block of PLL i created...

 

[leoren_tm]

Re: PLL fundamentals

realy???i was my first encounter..

 

[ahmad_abdulghany]

Re: PLL fundamentals

Try to model it also using verilog-a

 

[blowfish]

Re: PLL fundamentals

Hai leoren_tm,

please send me the pdf of Phase_locked_Loops_for_Wireless_Communications___Digital__Analog_and_Optical_Implementations.
I too require this book . Will this book be useful for DLLs also . I need information on charge pumps and voltage controlled delay lines(VCDL) .
Any help would be appreciated !

Added after 5 minutes:

Hai leoren_tm,

I am trying to simulate digital DLLs using simulink , but i dont know much on how to use Simulink for DLL. Can you send me the steps or procedures or any materials which shows the concept or method involved in DLL design using simulink.

 

[raghu_836]

Re: PLL fundamentals

/n blcok refers to countdown/up counter inorger to track the fundamental frequency.
so u can use it

 

[leoren_tm]

Re: PLL fundamentals

Hai leoren_tm,

please send me the pdf of Phase_locked_Loops_for_Wireless_Communications___Digital__Analog_and_Optical_Implementations.
I too require this book . Will this book be useful for DLLs also . I need information on charge pumps and voltage controlled delay lines(VCDL) .
Any help would be appreciated !

Added after 5 minutes:

Hai leoren_tm,

I am trying to simulate digital DLLs using simulink , but i dont know much on how to use Simulink for DLL. Can you send me the steps or procedures or any materials which shows the concept or method involved in DLL design using simulink.

i got busy on my thesis now..
kindly seach this site for tutorials..i xur ull find one...
didnt try DLL