How do you think about structural ASIC and CSOC ?

There are so many different concepts and implementation on structural ASIC/Csoc, how do you think about it ?

From my opinion, standard core cells, just like FPGA cell, together with serveral IPs(DRAM controller, cpu, ram block, Bus controller), connected by fixed-pattern metal mask with one/two programmable vias would have prosperous future.

how do you think

Hi,

I am also interested in this topics, but from another angle. Structural ASIC seem to take over ASIC a few years ago. However, this does not seen to be the case now with the closure of some structural ASIC businesses, and Synplicity decide to stop development of structural related tool.

What is the main reason for the poor adoption of this methodology? Hard to decide what to put in the structural ASIC, too much external components compare to an ASIC, or something else?

Regards,
Eng Han

That's because there were none well-defined structural ASIC concepts up to now.
I believed a new implementation method of user's logic would arised. Its abnormal that so many $ was needed to just publish a little chip.

When it comes to fabrics such as CSOC, Structured ASIC, FPGA, Standard Cells (Cell-based), SOGs and GAs, it really comes down to the following factors:
1. Kind of Application
2. Required Performance
3. NRE Cost
4. Availability of Expertise
5. IP Issues

Which is why after so many years, it is quite slow to face out some technologies, although it is quite clear that SOGs and GAs are slowly getting faced out.

We musn't forget at the moment, Structured ASIC is aimed to provide quick transfer or portability from rapid prototyping work in FPGA, thus giving reduced cost with improved power consumption and speed in Structured ASIC than FPGA.

CSOC is still aimed in SOC perspective to resolve issues in IP Cores and Management, power consumption, clock and power distribution and sometimes even the CMOS technology used. It has little relation to the fabric used, whether Structured ASIC or Standard Cell.

Even today, Standard Cell is still the dominant fabric used in current ASIC design flow used. Partly due to the EDA-CAD tools used by major and small design houses and standards adopted by foundries, and partly due to a good tradeoffs for competitive performance as a semi-custom ASIC.

May I ask a question?
what is the meaning of CSOC?

Configurable System on Chip

anyone would give out a example for CSoC?