How do you receive ASI?

[MaZiDium]

Hi

couple of months ago I tried to receive ASI using Xilinx cores in Spartan-6. I wasn't successful and then I got busy and now I have time again to work on that.

This is my first post here and I want to know how you receive ASI data using an FPGA? Do you use other ICs like Cypress CY7B923 or you receive the data using vhdl cores?
What if I want to receive multiple ASIs then the area and power for the external ICs become a problem and if not I think the cores take a lot of logic inside FPGA.

Thanks for considering my post.

Regards
Maz

 

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As an example of what resources it would take. Here is an ASI core for Xilinx from MVD 62 slices / 187 LUTs isn't very large.