how do u make D-flip flop ?

[thverda]

i made a simple D-flip flop.


=========================
module dff(Q,C,CE,CLR,D);

output Q;
input C;
input CE;
input CLR;
input D;
reg Q;
always@(posedge C)
Q=D;

endmodule


======================

but i wanna make a feedback D-flip flop.

 

[ads_ee]

Your not referring to this are you?
**broken link removed**

I would advise against doing this in an FPGA, or an ASIC (unless you're designing the cell library for said ASIC).

 

[thverda]

um. actually i want to make it. if u go to this site. u can see it.

https://cafe.naver.com/veryveryverilog/8


but i dont know how i make it . ( verilog)

input D;
output Q;

for example,

Q=D; this is possible.

but D=Q; this is not possible.

huhuhuhuhu....

 

[ads_ee]

your drawing translates to:

always @ (posedge c) Q <= ~Q;

...a divide by two.