DC is used for synthesis and its only for setup. so, if your DC constraints are only for setup; then you will have to define both setup and hold constraints for back-end. if input to DC is full constraints, then SDC from DC will do the job. back-end needs both setup and hold constraints, no matter whether dc/pt gives.
set_clock_transition : dont worry about this
set_clock_uncertainty : check your PLL jitter and set this to that value
set_clock_latency : This also does not matter much. so you can ignore this. But if u want to control the maximum clock tree insertion delay in back-end; you can provide this.