How do I use on chip memory to implement a finite state machine on a FPGA?

[fpganewb]

Could someone point me to some example verilog/vhdl code example that models a FSM which uses an explicit next state memory rather than if/else or case statments?

 

[lucbra]

I don't see the point why you would do this explicitely, but you'll have your reasons I suppose.

**broken link removed**