How do I prove the spec for column-parallel single slope ADC

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hyuugapatik

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column adc

Hi guys,

I am currently designing a column parallel single slope ADC for a CMOS image sensor.

I have done the DC, AC and Transient analysis. I am aware that I need to do .fft to determine the SNR and ENOB.

Are there any other simulations that I may have missed? Appreciate all the help I can get. Thank you all!

hyuuga_patik[/img]
 

single slope adc

You need to run Monte Carlo simulations to make sure variations between the different ADC channels are low. Otherwise you risk column fixed pattern noise in the images which is very bad.
 

Re: How do I prove the spec for column-parallel single slope

hi leili,

thanks for sharing!.. i will try that as soon as i am done with my fft sim

hyuugapatik
 

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