How do I load a hierarchical design in SOC Encounter?

[flyinmeteor]

I have all the abstracts (lef and lib) for all the blocks and a top level verilog file. However I tried to import the top level design to do floorplanning and i haven't had any luck. Can someone please help me?

Thanks.

 

[cop02ia]

Try be more specific with your problem, e.g:

What are the warning/errors?
What is the outcome so far?

Perhaps you might consider contacting Cadence support.

Best regards.