How do I load a hierarchical design in SOC Encounter?

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flyinmeteor

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I have all the abstracts (lef and lib) for all the blocks and a top level verilog file. However I tried to import the top level design to do floorplanning and i haven't had any luck. Can someone please help me?

Thanks.
 

Try be more specific with your problem, e.g:

What are the warning/errors?
What is the outcome so far?

Perhaps you might consider contacting Cadence support.

Best regards.
 

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