well, I don't want a pll because according to my 'short knowledge' it seems a bit necessary.
This brings up another related question.
When digital logics use different clock speeds, for interpolation, decimation, or fractional signal rate changes etc, where does the clock signals come from? Are they also generated from a dedicated PLL ? Than that just sounds like an aweful lot of PLLs for SoCs isn't it? How can I get those high speed clock signals that are used in interpoloation logics (CIC filter for example)?
and are the phase noise usually bad for these digital logics?