how do I change digital clock speed

[sharkies]

how can I change digital clock speed?
for instance if it's coming from a 30Mhz crystal, how can make the clock run at 200Mhz?
the digital clock speeds need to be increased by a fractional number.. but how?

thanks

 

[pauloynski]

Are you trying to overclock something? To increase the clock frequency in steps you need to use a PLL.

 

[sharkies]

anything other than that? I'm really trying to not use a PLL.
I don't need the frequency to vary, I just need the clock frequency to be a certain number higher than the crystal

 

[FvM]

You didn't yet manage to clarify in your posts, why you don't want a PLL. Effectively, all concurrent methods (some have been
mentioned elsewhere) involve a considerably higher circuit effort and possibly worse performance.

 

[sharkies]

well, I don't want a pll because according to my 'short knowledge' it seems a bit necessary.
This brings up another related question.
When digital logics use different clock speeds, for interpolation, decimation, or fractional signal rate changes etc, where does the clock signals come from? Are they also generated from a dedicated PLL ? Than that just sounds like an aweful lot of PLLs for SoCs isn't it? How can I get those high speed clock signals that are used in interpoloation logics (CIC filter for example)?
and are the phase noise usually bad for these digital logics?

 

[D Saurabh]

Typically what is done is a single PLL is used to output the highest frequency required by the digital and all other required frequencies are generated from the PLL output using clock divider circuitry. Hence a big SoC may have only 1 or 2 PLLs depending on the requirements and the rest are internally generated.

 

[sharkies]

Are those PLL(the ones for digital clocks) high specs as the ones that are used to generated carrier signals in the RF transceivers? or are they much simpler considering that the wanted signal that needs to be generated is much lower?