[SOLVED] How do a designer detect multi-cycle or false paths in design?

[er.akhilkumar]

Hello All,

Most of the time people ask how to find out multi-cycle or false paths in the design as we need to provide them to synthesis tool, they expect in the answers that the solution will be some tool. But, opposite to their expectation, people say that designers of the IP list down multi-cycle and false path. My question is how can a designer find out the multi-cycle paths and false paths in their designs?

Thanks
Akhil

 

[rca]

1- the designer who made the design could provide the paths which could be relax via false path or multi-cycle.
2- if your design meet the timing/area/power, you do need to add constraint.
3- if you are not able to reach the timing, you need to analyze the worst path and confirm, that a true path. if it is a true path, the design need to be modify to meet the timing or if it is a false path, you could apply a false path on this path.

 

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My question is how can a designer find out the multi-cycle paths and false paths in their designs?

Akhil,

IMHO, if an engineer doesn't know if multicycle paths exist in their design they aren't a designer, they are a coder. If I design some circuit in an FPGA or ASIC I KNOW if there are multicycle paths in the design and will add comments to the code and to the header of the file in a timing information section what those paths are, why they are multicycle, and the constraint required.

If the situation involves some legacy design written by coders then I would assume everything is single cycle and only analyze sections which seem impossible to meet timing. Those sections usually involve some enabled registers with lots of combinational logic between the registers.

Regards

 

[er.akhilkumar]

Thanks for the reply ads-ee. Can you please suggest me a good book to start with for going towards designer from coder?

Thanks again

Akhil,

IMHO, if an engineer doesn't know if multicycle paths exist in their design they aren't a designer, they are a coder. If I design some circuit in an FPGA or ASIC I KNOW if there are multicycle paths in the design and will add comments to the code and to the header of the file in a timing information section what those paths are, why they are multicycle, and the constraint required.

If the situation involves some legacy design written by coders then I would assume everything is single cycle and only analyze sections which seem impossible to meet timing. Those sections usually involve some enabled registers with lots of combinational logic between the registers.

Regards

 

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er.akhilkumar,

Hard for me to suggest a book as I've always thought like a designer, even as far back as high school (perhaps even earlier). There are some practical books on VHDL and Verilg and how to write synthesizable code, but that's not really the same as designing something.

Design is a creative process, hence why I consider some engineers coders and others designers. The coders just pound out code (perhaps very good code), but they don't really go outside the box and come up with something new or a different approach that is either more efficient, faster, smaller, etc. Coders can seldom run ASIC/FPGA projects as the design lead, since they don't have a grasp of high level design and architecture. Some of that knowledge is gained through experience, but innate ability will accelerate the process.

I see engineering as a discipline similar to art. There are some that are prodigies like the Rembrandts and DaVincis, but there are more that just produce ads for products.

Regards

 

[er.akhilkumar]

er.akhilkumar,

Hard for me to suggest a book as I've always thought like a designer, even as far back as high school (perhaps even earlier). There are some practical books on VHDL and Verilg and how to write synthesizable code, but that's not really the same as designing something.

Design is a creative process, hence why I consider some engineers coders and others designers. The coders just pound out code (perhaps very good code), but they don't really go outside the box and come up with something new or a different approach that is either more efficient, faster, smaller, etc. Coders can seldom run ASIC/FPGA projects as the design lead, since they don't have a grasp of high level design and architecture. Some of that knowledge is gained through experience, but innate ability will accelerate the process.

I see engineering as a discipline similar to art. There are some that are prodigies like the Rembrandts and DaVincis, but there are more that just produce ads for products.

Regards

Thanks for your answer ads-ee.
In my view, creativity is an outcome of knowledge. I just want to know what procedure you follow to sense that the design has multi-cycle? Method surely depends on creativity but I will be grateful to you if you can explain one method which you ever followed.

Thanks again

 

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Thanks for your answer ads-ee.
In my view, creativity is an outcome of knowledge. I just want to know what procedure you follow to sense that the design has multi-cycle? Method surely depends on creativity but I will be grateful to you if you can explain one method which you ever followed.

Thanks again

Actually that's pretty easy to determine. Look for registers with clock enables that only only stay active for a single clock cycle.
Before you ask, Yes it means looking through every line of code to find them. Hence the reason I include comments in the file header that state if there are any multicycle paths in the module.

Regards

 

[er.akhilkumar]

Thankyou very much ads-ee, now I understand what need to be done.

Actually that's pretty easy to determine. Look for registers with clock enables that only only stay active for a single clock cycle.
Before you ask, Yes it means looking through every line of code to find them. Hence the reason I include comments in the file header that state if there are any multicycle paths in the module.

Regards