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how detect bus idle in i2c

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shastri.vs

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bus idle + i2c

Hi,
I am designing an i2c bus in vhdl.
My problems are:
1. How a master checks whether the bus is idle. In the spec it is given that if SDA and SCL both are high then master thinks that bus is idle and tries to assert START bit. But if already some master is communicating on the bus and the HIGH on SDA and SCL could also because of this other master transmitting.
2. Should the newly joining master wait till STOP bit, i.e condition when SDA goes high when SCL is high. If it has to wait then how long it should wait for STOP bit.

please help
 

FvM

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detect i2c bus status

Consult the I2C specification
 

shastri.vs

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detect i2c bus is idle

I have gone through many specs but could not understand. Can you please help me if you know how it is. Or can you give me a spec which explains it.
 

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i2c bus idle

I know only one basic I2C specification, it's from Philips/NXP. I mentioned it in response to one of your previous posts.
 

    shastri.vs

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shastri.vs

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i2c wait for idle

I got the answer in one of the nxp spec. I had earlier gone through it, but not completely. The answer was simple though. I just need to wait for some time duration which is mentioned in the spec.
I was just banging my head in confusion without reading the spec fully. My mistake.


Thanks friend.
 

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