shastri.vs
Member level 2
bus idle + i2c
Hi,
I am designing an i2c bus in vhdl.
My problems are:
1. How a master checks whether the bus is idle. In the spec it is given that if SDA and SCL both are high then master thinks that bus is idle and tries to assert START bit. But if already some master is communicating on the bus and the HIGH on SDA and SCL could also because of this other master transmitting.
2. Should the newly joining master wait till STOP bit, i.e condition when SDA goes high when SCL is high. If it has to wait then how long it should wait for STOP bit.
please help
Hi,
I am designing an i2c bus in vhdl.
My problems are:
1. How a master checks whether the bus is idle. In the spec it is given that if SDA and SCL both are high then master thinks that bus is idle and tries to assert START bit. But if already some master is communicating on the bus and the HIGH on SDA and SCL could also because of this other master transmitting.
2. Should the newly joining master wait till STOP bit, i.e condition when SDA goes high when SCL is high. If it has to wait then how long it should wait for STOP bit.
please help