How create a core_gen using vhdl

[rajavel.rv]

Hi Friends,
How i can generated a IP core from my own VHDL. I have one option Synthesis my VHDL code and get the .ngc file but its only using for ISE synthesis and simulation. But i want to generate a core for simulation in Modelsim. Anybody have a idea please help me.

 

[TrickyDicky]

If its your own VHDL, you can already use it in modelsim.

 

[rajavel.rv]

yes TrickyDicky, am used in modelsim, and am not mention any particular code, u taken any code in vhdl eg: am done projects for huffman decoder, fm_demodulation etc,. k.
How this project am modified to component of xilinx core in xilinx core generator software.