casual
Junior Member level 2
I have done the matlab sdomain analysis and set the PLL bandwidth accordingly.
how could I verify the PLL loop bandwidth in the schematic simulation?
Could i obtain H(s)=out/in, transfer function of the PLL to check PLL loop bandwidth & overshoot (OS)?
how could I verify the PLL loop bandwidth in the schematic simulation?
Could i obtain H(s)=out/in, transfer function of the PLL to check PLL loop bandwidth & overshoot (OS)?
