Re: how could I fix hold violations in my design ?
here are two violations, it tells the clock skew is larger than data delay.
BTW, all effort are set highest.
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Timing constraint: TS_fpga_clk_gen_inst_clk_hsx = PERIOD TIMEGRP
"fpga_clk_gen_inst_clk_hsx" TS_xti_pad * 2 HIGH 50%;
669893 items analyzed, 805 timing errors detected. (0 setup errors, 805 hold errors)
Minimum period is 23.817ns.
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Hold Violations: TS_fpga_clk_gen_inst_clk_hsx = PERIOD TIMEGRP "fpga_clk_gen_inst_clk_hsx" TS_xti_pad * 2 HIGH 50%;
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Hold Violation: -1.486ns (requirement - (clock path skew + uncertainty - data path))
Source: mango/corona/hsx_dxb/rch0_stage[16] (FF)
Destination: mango/corona/vd/vbrg/u_vbrg_es/u_vbrg_es_if/mst32_hrd[16] (FF)
Requirement: 0.000ns
Data Path Delay: 1.215ns (Levels of Logic = 0)
Positive Clock Path Skew: 2.701ns
Source Clock: fpga_clk_gen_inst.clk_hsx rising at 0.000ns
Destination Clock: fpga_clk_gen_inst.clk_hsx rising at 60.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: mango/corona/hsx_dxb/rch0_stage[16] to mango/corona/vd/vbrg/u_vbrg_es/u_vbrg_es_if/mst32_hrd[16]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X189Y166.YQ Tcko 0.313 mango/rch0_stage[16]
mango/corona/hsx_dxb/rch0_stage[16]
SLICE_X191Y141.BX net (fanout=5) 0.981 mango/rch0_stage[16]
SLICE_X191Y141.CLK Tckdi (-Th) 0.079 mango/corona/vd/vbrg/u_vbrg_es/u_vbrg_es_if/mst32_hrd[16]
mango/corona/vd/vbrg/u_vbrg_es/u_vbrg_es_if/mst32_hrd[16]
------------------------------------------------- ---------------------------
Total 1.215ns (0.234ns logic, 0.981ns route)
(19.3% logic, 80.7% route)
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Hold Violation: -1.385ns (requirement - (clock path skew + uncertainty - data path))
Source: mango/acorn/u_pci/pci_100/pci_isa/ctl_state[0] (FF)
Destination: mango/acorn/u_pci/pci_100/pci_isa/isa_oe_ (FF)
Requirement: 0.000ns
Data Path Delay: 4.144ns (Levels of Logic = 2)
Positive Clock Path Skew: 5.529ns
Source Clock: fpga_clk_gen_inst.clk_hsx rising at 0.000ns
Destination Clock: fpga_clk_gen_inst.clk_hsx rising at 60.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: mango/acorn/u_pci/pci_100/pci_isa/ctl_state[0] to mango/acorn/u_pci/pci_100/pci_isa/isa_oe_
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X111Y281.XQ Tcko 0.313 mango/acorn/u_pci/pci_100/pci_isa/ctl_state[0]
mango/acorn/u_pci/pci_100/pci_isa/ctl_state[0]
SLICE_X120Y275.F4 net (fanout=8) 0.954 mango/acorn/u_pci/pci_100/pci_isa/ctl_state[0]
SLICE_X120Y275.X Tilo 0.179 mango/acorn/u_pci/pci_100/pci_isa/I_524_0_i
mango/acorn/u_pci/pci_100/pci_isa/I_524_0
SLICE_X89Y193.F4 net (fanout=30) 2.819 mango/acorn/u_pci/pci_100/pci_isa/I_524_0_i
SLICE_X89Y193.CLK Tckf (-Th) 0.121 mango/acorn/io_memrd_int
mango/acorn/u_pci/pci_100/pci_isa/isa_oe_s_i
mango/acorn/u_pci/pci_100/pci_isa/isa_oe_
------------------------------------------------- ---------------------------
Total 4.144ns (0.371ns logic, 3.773ns route)
(9.0% logic, 91.0% route)
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