hbsustc
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Hi,
Currently I am using a large-area SiGe transistor to design a LNA chip, the bias current can be as large as 50mA. The emitter of the transistor is connected to the ground directly to provide a input matching and a good noise figure at the same time. (It is a large-area devices, so it is possible.)
The problem is due to the high package bondwire (about 1nH in this case), there is no purely ground for this LNA. It is true this bondwire inductor can be utilized to realize a noise matching and input matching , however, it is only feasible for a small-area transistor. For a large-area transistor, this bondwire inductor will deteriorate the noise figure considerably in the input matching case.
Now I am using a on-chip capacitor in series with this bondwire to create a ground as the attached figure. However, the lossy on-chip capacitor will increase the NF. So is there any other better method to solve this problem? Any suggestion is appreciated. Thanks a lot.
Currently I am using a large-area SiGe transistor to design a LNA chip, the bias current can be as large as 50mA. The emitter of the transistor is connected to the ground directly to provide a input matching and a good noise figure at the same time. (It is a large-area devices, so it is possible.)
The problem is due to the high package bondwire (about 1nH in this case), there is no purely ground for this LNA. It is true this bondwire inductor can be utilized to realize a noise matching and input matching , however, it is only feasible for a small-area transistor. For a large-area transistor, this bondwire inductor will deteriorate the noise figure considerably in the input matching case.
Now I am using a on-chip capacitor in series with this bondwire to create a ground as the attached figure. However, the lossy on-chip capacitor will increase the NF. So is there any other better method to solve this problem? Any suggestion is appreciated. Thanks a lot.