How Convert this system verilog code to verilog?

[panda1234]

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// 4.38: testbench example 2
 
module testbench2();
  reg  a, b, c, y;
 
  // instantiate device under test
  sillyfunction dut(a, b, c, y);
 
  // apply inputs one at a time
  // checking results
  initial begin
    a = 0; b = 0; c = 0; #10;
    if (y === 1) else $error("000 failed.");
    c = 1; #10;
    assert (y === 0) else $error("001 failed.");
    b = 1; c = 0; #10;
    assert (y === 0) else $error("010 failed.");
    c = 1; #10;
    assert (y === 0) else $error("011 failed.");
    a = 1; b = 0; c = 0; #10;
    assert (y === 1) else $error("100 failed.");
    c = 1; #10;
    assert (y === 1) else $error("101 failed.");
    b = 1; c = 0; #10;
    assert (y === 0) else $error("110 failed.");
    c = 1; #10;
    assert (y === 0) else $error("111 failed.");
  end
endmodule

---

 

[mrflibble]

Looks like assert is the only statement you need to take care of. Several options:

The "who cares" option. Any decent simulator will handle SV these days. So if your simulator supports SV you could just use SV for your testbench and verilog for sysnthesis.

The "oh alright, I will Read The Fine Manual" option. Read the SV LRM, and see what assert does. Then you write a function or task in pure verilog to do the exact same thing.

And the ever popular "Google It" option. There probably already are people that did the RTFM option, and with a bit of luck there's some useable code floating around on the net.

Furthermore, if you are really really (no, really!) stuck with verilog for your verification work and still need assertions and all that, I suggest you read a bit here: https://www.asic-world.com/verilog/assertions.html