How challenging is it to design a PLL with 50ps Jitter and 100MHz clock output?

[chanchg]

Hello Everybody,

How challenging is to design a PLL with 50ps Jitter and 100MHz clock output?
Process could be either 0.18u or 0.35u.

Regards,

 

[sutapanaki]

Re: PLL Design

do you mean 50ps peak-to-peak jitter or 50ps rms jitter?

 

[chanchg]

Re: PLL Design

do you mean 50ps peak-to-peak jitter or 50ps rms jitter?

50ps peak-to-peak Jitter

 

[sutapanaki]

Re: PLL Design

I think 50ps p2p is a bit agressive. Look in the IEEE publication if it was done before. What supply noise do you expect?

 

[dumbfrog]

Re: PLL Design

narrow band and using 0.18u

 

[amarnath]

PLL Design

can someone tell me how to calculate jitter .i have simulated a pll in cadence.now i need to calculate the various jitter metrics (long term jitter etc).also if there is a method to remove the ripple in the vco control voltage due to the up and down signals (the up and down keep going high for a short time even when the pll is locked),then is it a good work or should they be allowed (razavi's chapter on pll's says up and down signals going high for a short time reduces the dead band when pll is in lock).

regards
amarnath

 

[nibo_mmx]

Re: PLL Design

please refer to www.designers-guide.com

it has the complete solution for calculating jitter and pnoise for pll

 

[amarnath]

PLL Design

i think instead of going in for a behavioral model.in spectre if u plot the eye-daigram,for the time when the pll has acquired lock to the end of the transient simulation time then u can use the information to calculate long term jtter etc.

regards
amarnath

 

[Btrend]

Re: PLL Design

if the vco is implemented as CMOS ring oscillator, I think 50ps p2p is too difficult.
if the vco is implemented as LC oscillator , maybe the phase noise of clock can be reduced. that's my opinion. hope it helps.

 

[nibo_mmx]

Re: PLL Design

Hey amarnath,

I am interested in how to calculate p2p or rms jitter by the eye-diagram plot? Could you give us more details about it.
I am also working on the design of PLL, but wonder how to calculate the jitter.

Thanks in advance

 

[amarnath]

PLL Design

hello nibo_mmx



refer to this link i have posted the info there.

regards
amarnath

 

[longjian]

PLL Design

you must reduce the power supply noise

 

[zouwanghui]

Re: PLL Design

I dont think you can calculate jitter using simulation. You can only estimate using models (Hajimiri or Razavi) by introducing major noise source (VCO noise & supply noise). And it is not easy to get 50ps c-2-c jitter using CMOS ring oscillator.

 

[amarnath]

PLL Design

yes that is true to a certaion extent.if u want to estimate the real time performance of the pll then u need to use these equations in those papers to characterize jitter due to vco.

regards
amarnath

 

[layes2]

Re: PLL Design

a think you mean p-p 50 ps
you must use regulator

 

[inquisitive]

Re: PLL Design

I have a PLL diesign with a ring oscillor (CMOS) already in place. I want to put a regulator to reduce supply noise to VCO. What regulator configuration should i use? I cant have much voltage drop on the regulated voltage so that my VCO works correctly. I cant use use an LDO since i cant use an external CAP for compensation. Please suggest.
Can u suggest some reading for this?

Added after 49 minutes:

to add to above, the VCO runs at 800Mhz and the power supply is 3.3V